1########################################################### 2## Commands for running tblgen to compile a td file 3########################################################## 4define transform-td-to-out 5$(if $(LOCAL_IS_HOST_MODULE), \ 6 $(call transform-host-td-to-out,$(1)), \ 7 $(call transform-device-td-to-out,$(1))) 8endef 9 10########################################################### 11## TableGen: Compile .td files to .inc. 12########################################################### 13 14# Set LOCAL_MODULE_CLASS to STATIC_LIBRARIES default (require 15# for macro local-intermediates-dir) 16ifeq ($(LOCAL_MODULE_CLASS),) 17 LOCAL_MODULE_CLASS := STATIC_LIBRARIES 18endif 19 20ifneq ($(strip $(TBLGEN_TABLES)),) 21 22intermediates := $(call local-intermediates-dir) 23tblgen_gen_tables := $(addprefix $(intermediates)/,$(TBLGEN_TABLES)) 24LOCAL_GENERATED_SOURCES += $(tblgen_gen_tables) 25 26tblgen_source_dir := $(LOCAL_PATH) 27ifneq ($(TBLGEN_TD_DIR),) 28tblgen_source_dir := $(TBLGEN_TD_DIR) 29endif 30 31# 32# The directory and the .td directory is not the same. 33# 34ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/ARM/MCTargetDesc) 35$(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN) 36 $(call transform-td-to-out, register-info) 37$(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN) 38 $(call transform-td-to-out,instr-info) 39$(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN) 40 $(call transform-td-to-out,subtarget) 41endif 42 43ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/X86/MCTargetDesc) 44$(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN) 45 $(call transform-td-to-out, register-info) 46$(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN) 47 $(call transform-td-to-out,instr-info) 48$(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td $(TBLGEN) 49 $(call transform-td-to-out,subtarget) 50endif 51 52 53ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),) 54$(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 55 $(call transform-td-to-out,register-info) 56endif 57 58ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),) 59$(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 60 $(call transform-td-to-out,instr-info) 61endif 62 63ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),) 64$(intermediates)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 65 $(call transform-td-to-out,asm-writer) 66endif 67 68ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),) 69$(intermediates)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 70 $(call transform-td-to-out,asm-writer -asmwriternum=1) 71endif 72 73ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),) 74$(intermediates)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 75 $(call transform-td-to-out,asm-matcher) 76endif 77 78ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),) 79$(intermediates)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 80 $(call transform-td-to-out,emitter) 81endif 82 83ifneq ($(filter %GenMCCodeEmitter.inc,$(tblgen_gen_tables)),) 84$(intermediates)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 85 $(call transform-td-to-out,emitter -mc-emitter) 86endif 87 88ifneq ($(filter %GenMCPseudoLowering.inc,$(tblgen_gen_tables)),) 89$(intermediates)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 90 $(call transform-td-to-out,pseudo-lowering) 91endif 92 93ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),) 94$(intermediates)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 95 $(call transform-td-to-out,dag-isel) 96endif 97 98ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),) 99$(intermediates)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 100 $(call transform-td-to-out,disassembler) 101endif 102 103ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),) 104$(intermediates)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 105 $(call transform-td-to-out,enhanced-disassembly-info) 106endif 107 108ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),) 109$(intermediates)/%GenFastISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 110 $(call transform-td-to-out,fast-isel) 111endif 112 113ifneq ($(filter %GenSubtargetInfo.inc,$(tblgen_gen_tables)),) 114$(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 115 $(call transform-td-to-out,subtarget) 116endif 117 118ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),) 119$(intermediates)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 120 $(call transform-td-to-out,callingconv) 121endif 122 123ifneq ($(filter %GenIntrinsics.inc,$(tblgen_gen_tables)),) 124$(intermediates)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td $(TBLGEN) 125 $(call transform-td-to-out,tgt_intrinsics) 126endif 127 128ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),) 129$(intermediates)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td $(TBLGEN) 130 $(call transform-td-to-out,arm-decoder) 131endif 132 133endif 134