1 /* 2 * Copyright (c) 2008, Google Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef MSM7K_SHARED_H 30 #define MSM7K_SHARED_H 31 32 #define MSM7K_SHARED_PHYS 0x01F00000 33 34 #define MSM7K_VERSION (MSM7K_SHARED_PHYS + 0x40) 35 36 #define VERSION_QDSP6 4 37 #define VERSION_APPS_SBL 6 38 #define VERSION_MODEM_SBL 7 39 #define VERSION_APPS 8 40 #define VERSION_MODEM 9 41 42 void get_version_modem(char *s); 43 void get_version_modem_sbl(char *s); 44 45 46 #define ACPU_CLK 0 /* Applications processor clock */ 47 #define ADM_CLK 1 /* Applications data mover clock */ 48 #define ADSP_CLK 2 /* ADSP clock */ 49 #define EBI1_CLK 3 /* External bus interface 1 clock */ 50 #define EBI2_CLK 4 /* External bus interface 2 clock */ 51 #define ECODEC_CLK 5 /* External CODEC clock */ 52 #define EMDH_CLK 6 /* External MDDI host clock */ 53 #define GP_CLK 7 /* General purpose clock */ 54 #define GRP_CLK 8 /* Graphics clock */ 55 #define I2C_CLK 9 /* I2C clock */ 56 #define ICODEC_RX_CLK 10 /* Internal CODEX RX clock */ 57 #define ICODEC_TX_CLK 11 /* Internal CODEX TX clock */ 58 #define IMEM_CLK 12 /* Internal graphics memory clock */ 59 #define MDC_CLK 13 /* MDDI client clock */ 60 #define MDP_CLK 14 /* Mobile display processor clock */ 61 #define PBUS_CLK 15 /* Peripheral bus clock */ 62 #define PCM_CLK 16 /* PCM clock */ 63 #define PMDH_CLK 17 /* Primary MDDI host clock */ 64 #define SDAC_CLK 18 /* Stereo DAC clock */ 65 #define SDC1_CLK 19 /* Secure Digital Card clocks */ 66 #define SDC1_PCLK 20 67 #define SDC2_CLK 21 68 #define SDC2_PCLK 22 69 #define SDC3_CLK 23 70 #define SDC3_PCLK 24 71 #define SDC4_CLK 25 72 #define SDC4_PCLK 26 73 #define TSIF_CLK 27 /* Transport Stream Interface clocks */ 74 #define TSIF_REF_CLK 28 75 #define TV_DAC_CLK 29 /* TV clocks */ 76 #define TV_ENC_CLK 30 77 #define UART1_CLK 31 /* UART clocks */ 78 #define UART2_CLK 32 79 #define UART3_CLK 33 80 #define UART1DM_CLK 34 81 #define UART2DM_CLK 35 82 #define USB_HS_CLK 36 /* High speed USB core clock */ 83 #define USB_HS_PCLK 37 /* High speed USB pbus clock */ 84 #define USB_OTG_CLK 38 /* Full speed USB clock */ 85 #define VDC_CLK 39 /* Video controller clock */ 86 #define VFE_CLK 40 /* Camera / Video Front End clock */ 87 #define VFE_MDC_CLK 41 /* VFE MDDI client clock */ 88 89 enum 90 { 91 VREG_MSMA_ID, 92 VREG_MSMP_ID, 93 VREG_MSME1_ID, /* Not supported in Panoramix */ 94 VREG_MSMC1_ID, /* Not supported in PM6620 */ 95 VREG_MSMC2_ID, /* Supported in PM7500 only */ 96 VREG_GP3_ID, /* Supported in PM7500 only */ 97 VREG_MSME2_ID, /* Supported in PM7500 and Panoramix only */ 98 VREG_GP4_ID, /* Supported in PM7500 only */ 99 VREG_GP1_ID, /* Supported in PM7500 only */ 100 VREG_TCXO_ID, 101 VREG_PA_ID, 102 VREG_RFTX_ID, 103 VREG_RFRX1_ID, 104 VREG_RFRX2_ID, 105 VREG_SYNT_ID, 106 VREG_WLAN_ID, 107 VREG_USB_ID, 108 VREG_BOOST_ID, 109 VREG_MMC_ID, 110 VREG_RUIM_ID, 111 VREG_MSMC0_ID, /* Supported in PM6610 only */ 112 VREG_GP2_ID, /* Supported in PM7500 only */ 113 VREG_GP5_ID, /* Supported in PM7500 only */ 114 VREG_GP6_ID, /* Supported in PM7500 only */ 115 VREG_RF_ID, 116 VREG_RF_VCO_ID, 117 VREG_MPLL_ID, 118 VREG_S2_ID, 119 VREG_S3_ID, 120 VREG_RFUBM_ID, 121 VREG_NCP_ID, 122 }; 123 124 int clock_enable(unsigned id); 125 int clock_disable(unsigned id); 126 int clock_set_rate(unsigned id, unsigned hz); 127 int clock_get_rate(unsigned id); 128 129 int vreg_enable(unsigned id); 130 int vreg_disable(unsigned id); 131 int vreg_set_level(unsigned id, unsigned mv); 132 133 void reboot(void); 134 135 #endif 136