| /external/llvm/test/CodeGen/Alpha/ |
| D | add128.ll | 1 ;test for ADDC and ADDE expansion
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelDAGToDAG.cpp | 334 case ISD::ADDE: { in Select()
337 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in Select()
342 if (Opcode == ISD::ADDE) { in Select()
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| D | MipsISelLowering.cpp | 179 setTargetDAGCombine(ISD::ADDE); in MipsTargetLowering()
501 case ISD::ADDE: in PerformDAGCombine()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 217 ADDE, SUBE, enumerator
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| D | SelectionDAG.h | 889 case ISD::ADDE: return true;
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| /external/llvm/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 97 setOperationAction(ISD::ADDE, MVT::i32, Custom); in BlackfinTargetLowering()
427 unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB; in LowerADDE()
469 case ISD::ADDE: in LowerOperation()
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| /external/qemu/tcg/ppc/ |
| D | tcg-target.c | 346 #define ADDE XO31(138) macro
1617 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5])); in tcg_out_op()
1622 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5])); in tcg_out_op()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 1086 case ISD::ADDE: in ExpandIntegerResult()
1225 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3); in ExpandShiftByConstant()
1468 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUB()
1517 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUBC()
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| D | SelectionDAG.cpp | 1959 case ISD::ADDE: { in ComputeMaskedBits()
3025 case ISD::ADDE: in getNode()
5911 case ISD::ADDE: return "adde"; in getOperationName()
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| D | DAGCombiner.cpp | 1052 case ISD::ADDE: return visitADDE(N); in visit()
1537 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), in visitADDE()
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| /external/llvm/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 102 setOperationAction(ISD::ADDE , MVT::i64, Expand); in AlphaTargetLowering()
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| /external/qemu/tcg/ppc64/ |
| D | tcg-target.c | 336 #define ADDE XO31(138) macro
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 89 setOperationAction(ISD::ADDE, MVT::i32, Expand); in XCoreTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 330 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 317 case ISD::ADDE: in IsProfitableToFold()
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| D | X86ISelLowering.cpp | 400 setOperationAction(ISD::ADDE, VT, Custom); in X86TargetLowering()
9275 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
9352 case ISD::ADDE: in LowerOperation()
9393 case ISD::ADDE: in ReplaceNodeResults()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 1195 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
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| /external/icu4c/test/testdata/ |
| D | NormalizationTest-3.2.0.txt | 2731 ADDE;ADDE;1100 1172 11A9;ADDE;1100 1172 11A9;
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| /external/icu4c/data/unidata/ |
| D | NormalizationTest.txt | 2881 ADDE;ADDE;1100 1172 11A9;ADDE;1100 1172 11A9;
|