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Searched refs:COPY_TO_REGCLASS (Results 1 – 16 of 16) sorted by relevance

/external/llvm/lib/Target/CellSPU/
DSPU64InstrInfo.td57 CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
58 (COPY_TO_REGCLASS R64C:$rB, VECREG))), 0xb)>;
70 def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CEQr64compare.Fragment, R32C))>;
71 def v2i64: CodeFrag<(i32 (COPY_TO_REGCLASS CEQv2i64compare.Fragment, R32C))>;
74 def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
76 def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
94 CodeFrag<(CLGTv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
95 (COPY_TO_REGCLASS R64C:$rB, VECREG))>;
98 CodeFrag<(CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
99 (COPY_TO_REGCLASS R64C:$rB, VECREG))>;
[all …]
DSPUISelDAGToDAG.cpp766 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT, in Select()
850 Result = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VT, in Select()
923 VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT, in SelectSHLi64()
968 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSHLi64()
990 VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT, in SelectSRLi64()
1037 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRLi64()
1059 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRAi64()
1067 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRAi64()
1115 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRAi64()
1143 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT, in SelectI64Constant()
[all …]
DSPUInstrInfo.td1428 (COPY_TO_REGCLASS R8C:$rA, VECREG)>;
1431 (COPY_TO_REGCLASS R16C:$rA, VECREG)>;
1434 (COPY_TO_REGCLASS R32C:$rA, VECREG)>;
1437 (COPY_TO_REGCLASS R64C:$rA, VECREG)>;
1440 (COPY_TO_REGCLASS R32FP:$rA, VECREG)>;
1443 (COPY_TO_REGCLASS R64FP:$rA, VECREG)>;
1446 (COPY_TO_REGCLASS (v16i8 VECREG:$rA), R8C)>;
1449 (COPY_TO_REGCLASS (v8i16 VECREG:$rA), R16C)>;
1452 (COPY_TO_REGCLASS (v4i32 VECREG:$rA), R32C)>;
1455 (COPY_TO_REGCLASS (v2i64 VECREG:$rA), R64C)>;
[all …]
DSPUISelLowering.cpp2751 SDValue extended = SDValue(DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, in LowerSIGN_EXTEND()
/external/llvm/include/llvm/Target/
DTargetOpcodes.h66 COPY_TO_REGCLASS = 10, enumerator
DTarget.td654 def COPY_TO_REGCLASS : Instruction {
/external/llvm/lib/Target/X86/
DX86InstrCompiler.td1162 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1169 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1197 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1204 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1236 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1240 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1258 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1262 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1268 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1273 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
[all …]
DX86InstrFPStack.td633 def : Pat<(f64 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,
635 def : Pat<(f80 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>,
637 def : Pat<(f80 (fextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>,
643 def : Pat<(f32 (fround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>,
645 def : Pat<(f32 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>,
647 def : Pat<(f64 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>,
DX86ISelDAGToDAG.cpp2134 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, in Select()
2164 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, in Select()
/external/llvm/lib/Target/Blackfin/
DBlackfinISelDAGToDAG.cpp169 DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, in FixRegisterClasses()
DBlackfinInstrInfo.td470 (STORE16pi (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS D:$val, D)),
474 (STORE16pi (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS D:$val, D)),
479 (i16 (COPY_TO_REGCLASS D16L:$val, D16L)),
530 (i16 (COPY_TO_REGCLASS D16L:$src, D16L)),
862 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS D:$src, D)), lo16)>;
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td4345 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4348 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4403 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4406 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4826 (v2f32 (COPY_TO_REGCLASS (Inst
4828 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4834 (v2f32 (COPY_TO_REGCLASS (Inst
4836 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4839 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4845 (v2f32 (COPY_TO_REGCLASS (Inst
[all …]
DARMInstrVFP.td393 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
400 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp656 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { in EmitMachineNode()
DScheduleDAGRRList.cpp2822 TargetOpcode::COPY_TO_REGCLASS) in AddPseudoTwoAddrDeps()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.td1460 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1462 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1465 (COPY_TO_REGCLASS F4RC:$src, F8RC)>;