| /external/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 931 Inst.addOperand(MCOperand::CreateImm(pred)); in populateADROperands()
1134 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitInstruction()
1156 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitInstruction()
1165 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitInstruction()
1179 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitInstruction()
1191 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitInstruction()
1228 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitInstruction()
1265 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitInstruction()
1290 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitInstruction()
1313 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm())); in EmitInstruction()
[all …]
|
| D | ARMMCInstLower.cpp | 81 MCOp = MCOperand::CreateImm(MO.getImm()); in lowerOperand()
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ThumbDisassemblerCore.h | 413 MI.addOperand(MCOperand::CreateImm(Imm)); in DisassembleThumb1General()
571 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn) << 2)); in DisassembleThumb1LdPC()
618 MI.addOperand(MCOperand::CreateImm(decodeImm12(insn))); in DisassembleThumb2Ldpci()
661 MI.addOperand(MCOperand::CreateImm(getT1Imm5(insn))); in DisassembleThumb1LdSt()
697 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn))); in DisassembleThumb1LdStSP()
722 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn))); in DisassembleThumb1AddPCi()
750 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn))); in DisassembleThumb1AddSPi()
827 MI.addOperand(MCOperand::CreateImm(getT1Imm7(insn))); in DisassembleThumb1Misc()
838 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 4))); in DisassembleThumb1Misc()
841 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); in DisassembleThumb1Misc()
[all …]
|
| D | ARMDisassemblerCore.cpp | 728 MI.addOperand(MCOperand::CreateImm(coproc)); in DisassembleCoprocessor()
735 MI.addOperand(MCOperand::CreateImm(decodeRd(insn))); in DisassembleCoprocessor()
749 MI.addOperand(MCOperand::CreateImm(Offset)); in DisassembleCoprocessor()
752 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 0))); in DisassembleCoprocessor()
756 MI.addOperand(MCOperand::CreateImm(OneCopOpc ? GetCopOpc(insn) in DisassembleCoprocessor()
761 MI.addOperand(NoGPR ? MCOperand::CreateImm(decodeRd(insn)) in DisassembleCoprocessor()
771 : MCOperand::CreateImm(decodeRn(insn))); in DisassembleCoprocessor()
773 MI.addOperand(MCOperand::CreateImm(decodeRm(insn))); in DisassembleCoprocessor()
778 MI.addOperand(MCOperand::CreateImm(GetCopOpc2(insn))); in DisassembleCoprocessor()
833 MI.addOperand(MCOperand::CreateImm(slice(insn, 22, 22) << 4 /* R Bit */ | in DisassembleBrFrm()
[all …]
|
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.cpp | 558 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); in getInstruction()
563 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); in getInstruction()
571 instr.addOperand(MCOperand::CreateImm(insn&0x7FFF)); in getInstruction()
583 instr.addOperand(MCOperand::CreateImm(getIMM(insn))); in getInstruction()
588 instr.addOperand(MCOperand::CreateImm(insn&0x1F)); in getInstruction()
604 instr.addOperand(MCOperand::CreateImm(getIMM(insn))); in getInstruction()
618 instr.addOperand(MCOperand::CreateImm(getIMM(insn))); in getInstruction()
628 instr.addOperand(MCOperand::CreateImm(getIMM(insn))); in getInstruction()
636 instr.addOperand(MCOperand::CreateImm(getSHT(insn))); in getInstruction()
650 instr.addOperand(MCOperand::CreateImm(getFSL(insn))); in getInstruction()
[all …]
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 543 Inst.addOperand(MCOperand::CreateImm(0)); in addExpr()
545 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); in addExpr()
552 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); in addCondCodeOperands()
559 Inst.addOperand(MCOperand::CreateImm(getCoproc())); in addCoprocNumOperands()
564 Inst.addOperand(MCOperand::CreateImm(getCoproc())); in addCoprocRegOperands()
585 Inst.addOperand(MCOperand::CreateImm( in addShiftedRegOperands()
591 Inst.addOperand(MCOperand::CreateImm( in addShifterOperands()
653 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); in addMemBarrierOptOperands()
685 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(AMOpc, ShiftAmount, in addMemMode2Operands()
700 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::add, in addMemMode2Operands()
[all …]
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 209 mcInst.addOperand(MCOperand::CreateImm(immediate)); in translateImmediate()
307 scaleAmount = MCOperand::CreateImm(insn.sibScale); in translateRMMemory()
362 scaleAmount = MCOperand::CreateImm(1); in translateRMMemory()
365 displacement = MCOperand::CreateImm(insn.displacement); in translateRMMemory()
|
| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeMCInstLower.cpp | 132 MCOp = MCOperand::CreateImm(MO.getImm()); in Lower()
160 MCOp = MCOperand::CreateImm(Val); in Lower()
|
| D | MBlazeInstrInfo.cpp | 146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in AnalyzeBranch()
165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); in AnalyzeBranch()
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 72 MO.push_back(MachineOperand::CreateImm(Scale)); in getFullAddress()
79 MO.push_back(MachineOperand::CreateImm(Disp)); in getFullAddress()
|
| D | X86MCInstLower.cpp | 318 MCOp = MCOperand::CreateImm(MO.getImm()); in Lower()
546 LEA.addOperand(MCOperand::CreateImm(1)); // scale in LowerTlsAddr()
554 LEA.addOperand(MCOperand::CreateImm(1)); // scale in LowerTlsAddr()
|
| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| D | MBlazeAsmParser.cpp | 183 Inst.addOperand(MCOperand::CreateImm(0)); in addExpr()
185 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); in addExpr()
241 static MBlazeOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { in CreateImm() function
454 return MBlazeOperand::CreateImm(EVal, S, E); in ParseImmediate()
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 222 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
244 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 271 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); in addExpr()
289 Inst.addOperand(MCOperand::CreateImm(getMemScale())); in addMemOperands()
313 static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){ in CreateImm() function
495 return X86Operand::CreateImm(Val, Start, End); in ParseOperand()
703 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc)); in ParseInstruction()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsMCInstLower.cpp | 104 MCOp = MCOperand::CreateImm(MO.getImm()); in Lower()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430MCInstLower.cpp | 126 MCOp = MCOperand::CreateImm(MO.getImm()); in Lower()
|
| D | MSP430InstrInfo.cpp | 240 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 340 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); in AddOperand()
506 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); in EmitSubregNode()
513 MI->addOperand(MachineOperand::CreateImm(SubIdx)); in EmitSubregNode()
830 MI->addOperand(MachineOperand::CreateImm(ExtraInfo)); in EmitSpecialNode()
838 MI->addOperand(MachineOperand::CreateImm(Flags)); in EmitSpecialNode()
|
| /external/llvm/include/llvm/MC/ |
| D | MCInst.h | 103 static MCOperand CreateImm(int64_t Val) { in CreateImm() function
|
| /external/llvm/lib/Target/PTX/ |
| D | PTXInstrInfo.cpp | 164 Pred.push_back(MachineOperand::CreateImm(PTX::PRED_NORMAL)); in DefinesPredicate()
387 MI->addOperand(MachineOperand::CreateImm(PTX::PRED_NORMAL)); in AddDefaultPredicate()
|
| /external/llvm/lib/Target/CellSPU/ |
| D | SPUInstrInfo.cpp | 246 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in AnalyzeBranch()
267 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); in AnalyzeBranch()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCMCInstLower.cpp | 149 MCOp = MCOperand::CreateImm(MO.getImm()); in LowerPPCMachineInstrToMCInst()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 76 MI->addOperand(MachineOperand::CreateImm(Val)); in addImm()
|
| D | MachineOperand.h | 447 static MachineOperand CreateImm(int64_t Val) { in CreateImm() function
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.cpp | 208 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
|