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Searched refs:Defs (Results 1 – 25 of 55) sorted by relevance

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/external/llvm/lib/Target/ARM/
DThumb2ITBlockPass.cpp45 SmallSet<unsigned, 4> &Defs,
56 SmallSet<unsigned, 4> &Defs, in TrackDefUses() argument
85 Defs.insert(Reg); in TrackDefUses()
88 Defs.insert(*Subreg); in TrackDefUses()
109 SmallSet<unsigned, 4> &Defs, in MoveCopyOutOfITBlock() argument
124 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
145 SmallSet<unsigned, 4> Defs; in InsertITInstructions() local
158 Defs.clear(); in InsertITInstructions()
160 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
197 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
[all …]
DNEONMoveFix.cpp53 RegMap Defs; in InsertMoves() local
70 RegMap::iterator DefMI = Defs.find(SrcReg); in InsertMoves()
71 if (DefMI != Defs.end()) { in InsertMoves()
114 Defs[MOReg] = MI; in InsertMoves()
117 Defs[*R] = MI; in InsertMoves()
DARMInstrThumb.td198 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
389 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
440 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
479 let Defs = [LR] in
532 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
542 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
759 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
769 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
930 let isCompare = 1, Defs = [CPSR] in {
945 } // isCompare = 1, Defs = [CPSR]
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/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td46 // AL is really implied by AX, but the registers in Defs must match the
48 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
56 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
61 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
70 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
80 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
85 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
89 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
95 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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DX86InstrSystem.td16 let Defs = [RAX, RDX] in
19 let Defs = [RAX, RCX, RDX] in
68 let Defs = [AL], Uses = [DX] in
71 let Defs = [AX], Uses = [DX] in
74 let Defs = [EAX], Uses = [DX] in
78 let Defs = [AL] in
81 let Defs = [AX] in
84 let Defs = [EAX] in
403 let Defs = [RDX, RAX], Uses = [RCX] in
411 let Defs = [RAX, RDI], Uses = [RDX, RDI] in
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DX86InstrExtension.td15 let Defs = [AX], Uses = [AL] in
18 let Defs = [EAX], Uses = [AX] in
22 let Defs = [AX,DX], Uses = [AX] in
25 let Defs = [EAX,EDX], Uses = [EAX] in
30 let Defs = [RAX], Uses = [EAX] in
34 let Defs = [RAX,RDX], Uses = [RAX] in
DX86InstrCompiler.td45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
88 let Defs = [EFLAGS] in
105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
139 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
164 let Defs = [EFLAGS], isCodeGenOnly=1,
178 let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
244 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
253 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
259 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
[all …]
DX86InstrControl.td141 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
180 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
215 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
247 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
269 let Defs = [RAX, R10, R11, RSP, EFLAGS],
280 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
DX86FloatingPoint.cpp860 unsigned Defs = Mask; in adjustLiveRegs() local
864 if (!(Defs & (1 << RegNo))) in adjustLiveRegs()
869 Defs &= ~(1 << RegNo); in adjustLiveRegs()
871 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?"); in adjustLiveRegs()
874 while (Kills && Defs) { in adjustLiveRegs()
876 unsigned DReg = CountTrailingZeros_32(Defs); in adjustLiveRegs()
881 Defs &= ~(1 << DReg); in adjustLiveRegs()
906 while(Defs) { in adjustLiveRegs()
907 unsigned DReg = CountTrailingZeros_32(Defs); in adjustLiveRegs()
911 Defs &= ~(1 << DReg); in adjustLiveRegs()
DX86InstrInfo.td614 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
618 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
626 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
668 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
683 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
692 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
695 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
701 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
706 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
724 let Defs = [EFLAGS] in {
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/external/llvm/lib/CodeGen/
DLiveVariables.cpp423 SmallVector<unsigned, 4> &Defs) { in HandlePhysRegDef() argument
462 Defs.push_back(Reg); // Remember this def. in HandlePhysRegDef()
466 SmallVector<unsigned, 4> &Defs) { in UpdatePhysRegDefs() argument
467 while (!Defs.empty()) { in UpdatePhysRegDefs()
468 unsigned Reg = Defs.back(); in UpdatePhysRegDefs()
469 Defs.pop_back(); in UpdatePhysRegDefs()
510 SmallVector<unsigned, 4> Defs; in runOnMachineFunction() local
515 HandlePhysRegDef(*II, 0, Defs); in runOnMachineFunction()
568 HandlePhysRegDef(MOReg, MI, Defs); in runOnMachineFunction()
570 UpdatePhysRegDefs(MI, Defs); in runOnMachineFunction()
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DStackSlotColoring.cpp143 SmallSet<unsigned, 4> &Defs,
429 SmallSet<unsigned, 4> &Defs = NewDefs[MBBId]; in ColorSlots() local
430 UnfoldAndRewriteInstruction(RefMIs[i], SS, NewFI, RC, Defs, MF); in ColorSlots()
613 SmallSet<unsigned, 4> &Defs, in UnfoldAndRewriteInstruction() argument
627 if (!Defs.count(Reg)) { in UnfoldAndRewriteInstruction()
631 Defs.insert(Reg); in UnfoldAndRewriteInstruction()
645 Defs.insert(Reg); in UnfoldAndRewriteInstruction()
656 if (!Defs.count(Reg)) in UnfoldAndRewriteInstruction()
660 Defs.insert(Reg); in UnfoldAndRewriteInstruction()
DScheduleDAGInstrs.cpp39 Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()), in ScheduleDAGInstrs()
222 assert(Defs[i].empty() && "Only BuildGraph should push/pop Defs"); in BuildSchedGraph()
265 std::vector<SUnit *> &DefList = Defs[Reg]; in BuildSchedGraph()
284 std::vector<SUnit *> &MemDefList = Defs[*Alias]; in BuildSchedGraph()
561 Defs[i].clear(); in BuildSchedGraph()
DLiveDebugVariables.cpp582 SmallVector<std::pair<SlotIndex, unsigned>, 16> Defs; in computeIntervals() local
587 Defs.push_back(std::make_pair(I.start(), I.value())); in computeIntervals()
590 for (unsigned i = 0; i != Defs.size(); ++i) { in computeIntervals()
591 SlotIndex Idx = Defs[i].first; in computeIntervals()
592 unsigned LocNo = Defs[i].second; in computeIntervals()
601 addDefsFromCopies(LI, LocNo, Kills, Defs, MRI, LIS); in computeIntervals()
/external/llvm/utils/TableGen/
DInstrInfoEmitter.cpp192 std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs"); in run() local
193 if (!Defs.empty()) { in run()
194 unsigned &IL = EmittedLists[Defs]; in run()
195 if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); in run()
DRecord.cpp1435 std::vector<Record*> Defs; in getValueAsListOfDefs() local
1438 Defs.push_back(DI->getDef()); in getValueAsListOfDefs()
1444 return Defs; in getValueAsListOfDefs()
1586 const std::map<std::string, Record*> &Defs = RK.getDefs(); in operator <<() local
1587 for (std::map<std::string, Record*>::const_iterator I = Defs.begin(), in operator <<()
1588 E = Defs.end(); I != E; ++I) in operator <<()
1603 std::vector<Record*> Defs; in getAllDerivedDefinitions() local
1607 Defs.push_back(I->second); in getAllDerivedDefinitions()
1609 return Defs; in getAllDerivedDefinitions()
/external/skia/src/svg/
DSkSVGDefs.cpp20 DEFINE_SVG_NO_INFO(Defs) in DEFINE_SVG_NO_INFO() argument
DSkSVGDefs.h24 DECLARE_SVG_INFO(Defs);
/external/llvm/include/llvm/CodeGen/
DLiveVariables.h171 SmallVector<unsigned, 4> &Defs);
172 void UpdatePhysRegDefs(MachineInstr *MI, SmallVector<unsigned, 4> &Defs);
/external/llvm/lib/Target/SystemZ/
DSystemZInstrFP.td100 let Defs = [PSW] in {
130 let Defs = [PSW] in {
168 } // Defs = [PSW]
267 let Defs = [PSW] in {
303 } // Defs = [PSW]
316 let Defs = [PSW] in {
332 } // Defs = [PSW]
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td62 let Defs = [LR8] in
69 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
95 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
133 let Defs = [CR0] in {
169 let Defs = [CR0] in
235 let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in {
241 let Defs = [X1], Uses = [X1] in
246 let Defs = [LR8] in {
330 let Defs = [CARRY] in {
346 let Defs = [CARRY] in {
[all …]
DPPCInstrInfo.td256 list<Register> Defs = [CR0];
363 let Defs = [R1], Uses = [R1] in {
374 let Defs = [R1], Uses = [R1] in
414 let Defs = [LR] in
436 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
461 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
552 let Defs = [CR0] in {
638 let Defs = [CR0] in
856 let Defs = [CARRY] in {
875 let Defs = [CARRY] in {
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/external/llvm/lib/Target/MBlaze/
DMBlazeInstrFSL.td127 let Defs = [CARRY] in {
166 let Defs = [CARRY] in {
197 let Defs = [CARRY] in {
220 let Defs = [CARRY] in {
/external/llvm/lib/Target/Blackfin/
DBlackfinInstrInfo.td136 let Defs = [SP], Uses = [SP] in {
169 Defs = [R0, R1, R2, R3, P0, P1, P2, LB0, LB1, LC0, LC1, RETS, ASTAT] in {
496 let Defs = [AZ, AN, AC0, V] in {
541 let Uses = [SP], Defs = [SP] in {
598 let Defs = [AC0] in
693 let Defs = [AZ, AN, V, VS],
702 let Defs = [AZ, AN, V, VS] in {
741 let Defs = [AZ, AN, AC0, V, VS] in {
769 let Defs = [AZ, AN, V, VS] in
782 let Defs = [AZ, AN, V] in
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.td212 let Defs = [O7] in {
216 let Defs = [O6], Uses = [O6] in {
467 let Defs = [ICC] in
478 let Defs = [ICC] in
481 let Uses = [ICC], Defs = [ICC] in
488 let Defs = [Y] in {
494 let Defs = [Y] in {
546 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
574 let Defs = [Y] in {
684 let Defs = [FCC] in {

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