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/external/qemu/distrib/sdl-1.2.12/src/hermes/
DHeadMMX.h81 #pragma aux ConvertMMX "_*" modify [EAX EBX ECX EDX ESI EDI]
83 #pragma aux ClearMMX_32 "_*" modify [EAX EBX ECX EDX ESI EDI]
84 #pragma aux ClearMMX_24 "_*" modify [EAX EBX ECX EDX ESI EDI]
85 #pragma aux ClearMMX_16 "_*" modify [EAX EBX ECX EDX ESI EDI]
86 #pragma aux ClearMMX_8 "_*" modify [EAX EBX ECX EDX ESI EDI]
DHeadX86.h138 #pragma aux ConvertX86 "_*" modify [EAX EBX ECX EDX ESI EDI]
139 #pragma aux ClearX86_32 "_*" modify [EAX EBX ECX EDX ESI EDI]
140 #pragma aux ClearX86_24 "_*" modify [EAX EBX ECX EDX ESI EDI]
141 #pragma aux ClearX86_16 "_*" modify [EAX EBX ECX EDX ESI EDI]
142 #pragma aux ClearX86_8 "_*" modify [EAX EBX ECX EDX ESI EDI]
/external/llvm/lib/Target/X86/
DX86Subtarget.cpp177 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; in AutoDetectSubtargetFeatures() local
186 X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); in AutoDetectSubtargetFeatures()
188 if ((EDX >> 15) & 1) HasCMov = true; ToggleFeature(X86::FeatureCMOV); in AutoDetectSubtargetFeatures()
189 if ((EDX >> 23) & 1) X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); in AutoDetectSubtargetFeatures()
190 if ((EDX >> 25) & 1) X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); in AutoDetectSubtargetFeatures()
191 if ((EDX >> 26) & 1) X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); in AutoDetectSubtargetFeatures()
222 X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); in AutoDetectSubtargetFeatures()
223 if ((EDX >> 29) & 0x1) { in AutoDetectSubtargetFeatures()
DX86CallingConv.td34 CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
82 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
147 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
200 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
301 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
314 // The first 2 integer arguments are passed in ECX/EDX
315 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
347 // The first 2 integer arguments are passed in ECX/EDX
348 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
DX86InstrArithmetic.td61 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
63 "mul{l}\t$src", // EAX,EDX = EAX*GR32
64 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/]>;
85 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
88 []>; // EAX,EDX = EAX*[mem32]
101 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
103 // EAX,EDX = EAX*GR32
115 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
117 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
250 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
[all …]
DX86RegisterInfo.td101 def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[-2, 2, 2]>;
125 def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
304 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
342 def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)> {
353 def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX)> {
381 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)> {
421 // A class to support the 'A' assembler constraint: EAX then EDX.
422 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)> {
DX86RegisterInfo.cpp84 case X86::EDX: case X86::R13: return 3; in getCompactUnwindRegNum()
334 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 in getCalleeSavedRegs()
648 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegister()
660 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegister()
697 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegister()
733 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegister()
734 return X86::EDX; in getX86SubSuperRegister()
769 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegister()
DREADME-SSE.txt200 %EDX = MOV32rm <fi#3>, 1, %NOREG, 0
201 ADD32rm %EAX<def&use>, %EDX, 1, %NOREG, 0
202 %EDX = MOV32rm <fi#7>, 1, %NOREG, 0
203 %EDX = MOV32rm %EDX, 1, %NOREG, 40
204 IMUL32rr %EAX<def&use>, %EDX
DX86InstrExtension.td25 let Defs = [EAX,EDX], Uses = [EAX] in
27 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
DX86InstrControl.td141 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
180 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
/external/llvm/lib/Support/
DHost.cpp109 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; in getHostCPUName() local
110 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) in getHostCPUName()
117 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); in getHostCPUName()
118 bool Em64T = (EDX >> 29) & 0x1; in getHostCPUName()
/external/llvm/test/CodeGen/X86/
D2008-09-17-inline-asm-1.ll4 ; %0 must not be put in EAX or EDX.
10 ; In the second asm, $0 and $2 must not be put in EDX.
Dabi-isel.ll1684 ; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[EDX:%e.x]]
1685 ; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
1693 ; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L24$pb([[EAX]]), [[EDX:%e.x]]
1694 ; DARWIN-32-PIC-NEXT: movl ([[EDX]],[[ECX]],4), [[EDX:%e.x]]
1696 ; DARWIN-32-PIC-NEXT: movl [[EDX]], ([[EAX]],[[ECX]],4)
1762 ; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, [[EDX:%e.x]]
1763 ; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
1771 ; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L25$pb([[EAX]]), [[EDX:%e.x]]
1772 ; DARWIN-32-PIC-NEXT: movl ([[EDX]],[[ECX]],4), [[EDX:%e.x]]
1774 ; DARWIN-32-PIC-NEXT: movl [[EDX]], ([[EAX]],[[ECX]],4)
[all …]
Dfast-cc-pass-in-regs.ll8 ; CHECK: mov{{.*}}EDX, 1
D2010-02-23-RematImplicitSubreg.ll9 ; sub-registers %DX and %EDX.
/external/qemu/target-i386/
Dexec.h39 #define EDX (env->regs[R_EDX]) macro
294 EDX = env->regs[R_EDX]; in env_to_regs()
322 env->regs[R_EDX] = EDX; in regs_to_env()
Dop_helper.c383 stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX); in switch_tss()
397 stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX); in switch_tss()
449 EDX = new_regs[2]; in switch_tss()
1427 stq_phys(sm_state + 0x7fe8, EDX); in do_smm_enter()
1456 stl_phys(sm_state + 0x7fd8, EDX); in do_smm_enter()
1553 EDX = ldq_phys(sm_state + 0x7fe8); in helper_rsm()
1586 EDX = ldl_phys(sm_state + 0x7fd8); in helper_rsm()
1677 num = (EAX & 0xffff) | ((EDX & 0xffff) << 16); in helper_divw_AX()
1688 EDX = (EDX & ~0xffff) | r; in helper_divw_AX()
1695 num = (EAX & 0xffff) | ((EDX & 0xffff) << 16); in helper_idivw_AX()
[all …]
/external/llvm/include/llvm/Support/
DSolaris.h28 #undef EDX
/external/kernel-headers/original/asm-x86/
Dptrace-abi.h8 #define EDX 2 macro
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.h39 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 enumerator
DX86MCTargetDesc.cpp131 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX; in getX86RegNum()
147 return N86::EDX; in getX86RegNum()
/external/llvm/test/TableGen/
DTargetInstrInfo.td42 def EDX;
146 def IN8rr : Inst<(ops), "in AL, EDX", 0xEC, RawFrm,
147 [(set AL, (unspec EDX))]>;
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h127 ENTRY(EDX) \
145 ENTRY(EDX) \
/external/valgrind/main/VEX/auxprogs/
Dgenoffsets.c85 GENOFFSET(X86,x86,EDX); in foo()
/external/valgrind/main/coregrind/m_sigframe/
Dsigframe-x86-linux.c378 SC2(edx,EDX); in synth_ucontext()

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