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Searched refs:HasBaseReg (Results 1 – 11 of 11) sorted by relevance

/external/llvm/lib/Transforms/Utils/
DAddrModeMatcher.cpp269 if (AddrMode.HasBaseReg) { in MatchOperationAddr()
274 AddrMode.HasBaseReg = true; in MatchOperationAddr()
285 if (AddrMode.HasBaseReg) in MatchOperationAddr()
287 AddrMode.HasBaseReg = true; in MatchOperationAddr()
354 if (!AddrMode.HasBaseReg) { in MatchAddr()
355 AddrMode.HasBaseReg = true; in MatchAddr()
360 AddrMode.HasBaseReg = false; in MatchAddr()
/external/llvm/include/llvm/Transforms/Utils/
DAddrModeMatcher.h46 (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale);
/external/llvm/lib/Target/X86/
DX86AsmPrinter.cpp287 bool HasBaseReg = BaseReg.getReg() != 0; in printLeaMemReference() local
288 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in printLeaMemReference()
290 HasBaseReg = false; in printLeaMemReference()
293 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
313 if (HasBaseReg) in printLeaMemReference()
DX86ISelLowering.cpp9641 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) in isLegalAddressingMode()
9663 if (AM.HasBaseReg) in isLegalAddressingMode()
/external/llvm/lib/Transforms/Scalar/
DLoopStrengthReduce.cpp303 AM.HasBaseReg = true; in InitialMatch()
309 AM.HasBaseReg = true; in InitialMatch()
371 if (AM.HasBaseReg && BaseRegs.empty()) { in print()
374 } else if (!AM.HasBaseReg && !BaseRegs.empty()) { in print()
1148 if (AM.Scale != 0 && AM.HasBaseReg && AM.BaseOffs != 0) in isLegalUse()
1200 bool HasBaseReg, in isAlwaysFoldable() argument
1211 AM.HasBaseReg = HasBaseReg; in isAlwaysFoldable()
1216 if (!AM.HasBaseReg && AM.Scale == 1) { in isAlwaysFoldable()
1218 AM.HasBaseReg = true; in isAlwaysFoldable()
1226 bool HasBaseReg, in isAlwaysFoldable() argument
[all …]
/external/llvm/include/llvm/Target/
DTargetLowering.h1475 bool HasBaseReg; member
1477 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} in AddrMode()
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp3245 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && AM.BaseOffs == 0) in isLegalAddressingMode()
3249 if (AM.BaseGV ==0 && AM.HasBaseReg && AM.Scale == 0 && isInt<14>(AM.BaseOffs)) in isLegalAddressingMode()
3253 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 1 && AM.BaseOffs ==0) in isLegalAddressingMode()
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp3207 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
3212 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1558 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp5653 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
5658 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp7221 if (((unsigned)AM.HasBaseReg + Scale) <= 2) in isLegalT2ScaledAddressingMode()
7279 if (((unsigned)AM.HasBaseReg + Scale) <= 2) in isLegalAddressingMode()