Searched refs:HasV6Ops (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARM.td | 103 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
108 [HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>;
173 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
174 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
176 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
177 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
179 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
180 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
184 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
|
| D | ARMSubtarget.cpp | 45 , HasV6Ops(false) in ARMSubtarget()
95 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true; in ARMSubtarget()
112 IsR9Reserved = ReserveR9 | !HasV6Ops; in ARMSubtarget()
|
| D | ARMSubtarget.h | 44 bool HasV6Ops; variable
179 bool hasV6Ops() const { return HasV6Ops; } in hasV6Ops()
|
| D | ARMInstrInfo.td | 157 AssemblerPredicate<"HasV6Ops">;
|