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Searched refs:INSERT_SUBREG (Results 1 – 14 of 14) sorted by relevance

/external/llvm/include/llvm/Target/
DTargetOpcodes.h49 INSERT_SUBREG = 7, enumerator
DTarget.td633 def INSERT_SUBREG : Instruction {
/external/llvm/test/CodeGen/Thumb2/
Dcrash.ll27 ; The first INSERT_SUBREG needs an <undef> use operand for that to work.
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h280 return getOpcode() == TargetOpcode::INSERT_SUBREG;
/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp637 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT, in Select()
718 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT, in Select()
DSystemZInstrInfo.td1092 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
1130 (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1136 (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1141 (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp1787 Opc == TargetOpcode::INSERT_SUBREG) in getNodePriority()
2004 Opc == TargetOpcode::INSERT_SUBREG || in UnscheduledNode()
2033 POpc == TargetOpcode::INSERT_SUBREG || in UnscheduledNode()
2502 Opc == TargetOpcode::INSERT_SUBREG) in canEnableCoalescing()
2837 SuccOpc == TargetOpcode::INSERT_SUBREG || in AddPseudoTwoAddrDeps()
DInstrEmitter.cpp477 } else if (Opc == TargetOpcode::INSERT_SUBREG || in EmitSubregNode()
649 Opc == TargetOpcode::INSERT_SUBREG || in EmitMachineNode()
DSelectionDAG.cpp5073 SDNode *Result = getMachineNode(TargetOpcode::INSERT_SUBREG, DL, in getTargetInsertSubreg()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td4384 (v16i8 (INSERT_SUBREG QPR:$src1,
4390 (v8i16 (INSERT_SUBREG QPR:$src1,
4396 (v4i32 (INSERT_SUBREG QPR:$src1,
4403 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4406 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4410 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4412 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4415 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4417 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4419 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
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/external/llvm/lib/Target/Blackfin/
DBlackfinInstrInfo.td478 (STORE8p (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
517 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
529 (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
/external/llvm/lib/Target/X86/
DX86InstrSSE.td136 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
177 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
180 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
186 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
DREADME.txt82 Note. any_extend is now turned into an INSERT_SUBREG. We still need to teach
DX86InstrCompiler.td1006 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;