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Searched refs:ImplicitDefs (Results 1 – 12 of 12) sorted by relevance

/external/llvm/include/llvm/MC/
DMCInstrDesc.h142 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr variable
232 return ImplicitDefs; in getImplicitDefs()
238 if (ImplicitDefs == 0) return 0; in getNumImplicitDefs()
240 for (; ImplicitDefs[i]; ++i) /*empty*/; in getNumImplicitDefs()
256 if (const unsigned *ImpDefs = ImplicitDefs) in hasImplicitDefOfPhysReg()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1112 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_r()
1134 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rr()
1158 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rrr()
1179 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_ri()
1202 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rii()
1223 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rf()
1247 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rri()
1263 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_i()
1280 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_ii()
DScheduleDAGFast.cpp426 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
509 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
511 for (const unsigned *Reg = MCID.ImplicitDefs; *Reg; ++Reg) { in DelayForLiveRegsBottomUp()
DScheduleDAGRRList.cpp1028 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
1112 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
1114 for (const unsigned *Reg = MCID.ImplicitDefs; *Reg; ++Reg) in DelayForLiveRegsBottomUp()
DScheduleDAGSDNodes.cpp117 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { in CheckForPhysRegDependency()
/external/llvm/utils/TableGen/
DCodeGenInstruction.cpp320 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
338 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
341 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
DCodeGenInstruction.h216 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
DDAGISelMatcherGen.cpp782 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
907 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
DCodeGenDAGPatterns.cpp1555 if (!InstInfo.ImplicitDefs.empty()) { in ApplyTypeConstraints()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp301 .addReg(II.ImplicitDefs[0])); in FastEmitInst_r()
323 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rr()
348 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rrr()
370 .addReg(II.ImplicitDefs[0])); in FastEmitInst_ri()
392 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rf()
417 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rri()
436 .addReg(II.ImplicitDefs[0])); in FastEmitInst_i()
456 .addReg(II.ImplicitDefs[0])); in FastEmitInst_ii()
DThumb2SizeReduction.cpp189 for (const unsigned *Regs = MCID.ImplicitDefs; *Regs; ++Regs) in HasImplicitCPSRDef()
/external/llvm/lib/CodeGen/
DMachineInstr.cpp475 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
476 for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs) in addImplicitDefUseOperands()