/external/tremolo/Tremolo/ |
D | dpen.s | 98 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit 123 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit 142 LDRB r14,[r12,r14,LSR #7] @ r14= t[chase+bit+1+(!bit || t[chase]0x0x80)] 153 MOV r6, r6, LSR #1 155 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit 180 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit 200 ADC r12,r8, r14,LSR #15 @ r12= 1+((chase+bit)<<1)+(!bit || t[chase]0x0x8000) 201 ADC r12,r12,r14,LSR #15 @ r12= t + (1+chase+bit+(!bit || t[chase]0x0x8000))<<1 213 MOVS r0, r0, LSR #1 @ r0 = lok>>1 C = bottom bit 298 MOV r8, r8, LSR r2 @ r8 = entry>>s->q_bits [all …]
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D | bitwiseARM.s | 57 MOV r10,r10,LSR r14 @ r10= ptr[0]>>(32-bitsLeftInWord) 81 MOV r10,r10,LSR r14 @ r10= first bitsLeftInWord bits 155 ADD r6,r10,r10,LSR #3 @ r6 = pointer to data 248 MOV r10,r10,LSR r14 @ r10= ptr[0]>>(32-bitsLeftInWord) 273 MOV r10,r10,LSR r14 @ r10= first bitsLeftInWord bits 395 ADD r6,r10,r10,LSR #3 @ r6 = pointer to data
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D | floor1ARM.s | 59 MOVS r6, r6, LSR #15
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/external/valgrind/main/coregrind/m_dispatch/ |
D | dispatch-arm-linux.S | 102 and r2, r1, r0, LSR #2 // r2 = entry # 147 and r2, r1, r0, LSR #2 // r2 = entry #
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/external/v8/test/cctest/ |
D | test-disasm-arm.cc | 136 COMPARE(rsb(r6, r7, Operand(fp, LSR, 1)), in TEST() 138 COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC), in TEST() 140 COMPARE(rsb(r6, r7, Operand(fp, LSR, 31), LeaveCC, pl), in TEST() 201 COMPARE(cmp(r7, Operand(r8, LSR, 3), gt), in TEST()
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/external/llvm/test/CodeGen/X86/ |
D | negative-stride-fptosi-user.ll | 3 ; LSR previously eliminated the sitofp by introducing an induction
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D | loop-hoist.ll | 1 ; LSR should hoist the load from the "Arr" stub out of the loop.
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D | lsr-nonaffine.ll | 3 ; LSR should leave non-affine expressions alone because it currently
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D | optimize-max-2.ll | 5 ; LSR's OptimizeMax function shouldn't try to eliminate this max, because
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D | lsr-delayed-fold.ll | 4 ; but LSR should tolerate this. 53 ; LSR ends up going into conservative pruning mode; don't prune the solution 136 ; LSR needs to remember inserted instructions even in postinc mode, because
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D | lsr-wrap.ll | 3 ; LSR would like to use a single IV for both of these, however it's
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D | lsr-overflow.ll | 4 ; The comparison uses the pre-inc value, which could lead LSR to
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D | lsr-redundant-addressing.ll | 4 ; LSR shouldn't create lots of redundant address computations.
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D | lsr-reuse-trunc.ll | 4 ; Full strength reduction wouldn't reduce register pressure, so LSR should
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D | optimize-max-1.ll | 3 ; LSR should be able to eliminate both smax and umax expressions
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D | optimize-max-3.ll | 4 ; LSR's OptimizeMax should eliminate the select (max).
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/external/llvm/test/Transforms/LoopStrengthReduce/ |
D | phi_node_update_multiple_preds.ll | 2 ; LSR should not crash on this.
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D | share_code_in_preheader.ll | 2 ; LSR should not make two copies of the Q*L expression in the preheader!
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D | uglygep.ll | 3 ; LSR shouldn't consider %t8 to be an interesting user of %t6, and it
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/external/ppp/pppd/ |
D | NOTICE | 202 Jean-Luc.Richier@imag.fr, IMAG-LSR. 206 Jean-Luc.Richier@imag.fr, IMAG-LSR. 231 sept laboratoires dont le laboratoire Logiciels, Syst�mes, R�seaux (LSR). 252 The research unit in Software, Systems, Networks (LSR) is member of IMAG.
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/external/sonivox/arm-hybrid-22k/lib_src/ |
D | ARM-E_interpolate_loop_gnu.s | 116 ADD pPhaseAccum, pPhaseAccum, tmp2, LSR #(NUM_PHASE_FRAC_BITS - NEXT_INPUT_PCM_SHIFT)
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D | ARM-E_interpolate_noloop_gnu.s | 108 ADD pPhaseAccum, pPhaseAccum, tmp2, LSR #(NUM_PHASE_FRAC_BITS - NEXT_INPUT_PCM_SHIFT)
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/external/sonivox/arm-wt-22k/lib_src/ |
D | ARM-E_interpolate_noloop_gnu.s | 108 ADD pPhaseAccum, pPhaseAccum, tmp2, LSR #(NUM_PHASE_FRAC_BITS - NEXT_INPUT_PCM_SHIFT)
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D | ARM-E_interpolate_loop_gnu.s | 116 ADD pPhaseAccum, pPhaseAccum, tmp2, LSR #(NUM_PHASE_FRAC_BITS - NEXT_INPUT_PCM_SHIFT)
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/external/v8/src/arm/ |
D | stub-cache-arm.cc | 1008 Operand(ival, LSR, kBitsPerInt - kBinary32MantissaBits)); in StoreIntAsFloat() 1038 __ orr(hiword, scratch, Operand(hiword, LSR, mantissa_shift_for_hi_word)); in GenerateUInt2Double() 2122 __ mov(r6, Operand(r6, LSR, HeapNumber::kMantissaBitsInTopWord)); in CompileMathFloorCall() 3495 __ ldrsb(value, MemOperand(r3, key, LSR, 1)); in CompileKeyedLoadStub() 3499 __ ldrb(value, MemOperand(r3, key, LSR, 1)); in CompileKeyedLoadStub() 3660 __ mov(r1, Operand(value, LSR, kBinary32MantissaBits)); in CompileKeyedLoadStub() 3688 __ orr(r2, r2, Operand(r0, LSR, kMantissaShiftForHiWord)); in CompileKeyedLoadStub() 3903 __ mov(r9, Operand(r9, LSR, HeapNumber::kExponentShift)); in CompileKeyedStoreStub() 3920 __ orr(r7, r7, Operand(r6, LSR, kMantissaInLoWordShift)); in CompileKeyedStoreStub() 3934 __ orr(r5, r9, Operand(r6, LSR, kMantissaInLoWordShift)); in CompileKeyedStoreStub() [all …]
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