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Searched refs:MCID (Results 1 – 25 of 49) sorted by relevance

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/external/llvm/include/llvm/MC/
DMCInstrDesc.h96 namespace MCID {
190 return Flags & (1 << MCID::Variadic); in isVariadic()
196 return Flags & (1 << MCID::HasOptionalDef); in hasOptionalDef()
278 return Flags & (1 << MCID::Return); in isReturn()
282 return Flags & (1 << MCID::Call); in isCall()
289 return Flags & (1 << MCID::Barrier); in isBarrier()
299 return Flags & (1 << MCID::Terminator); in isTerminator()
307 return Flags & (1 << MCID::Branch); in isBranch()
313 return Flags & (1 << MCID::IndirectBranch); in isIndirectBranch()
337 return Flags & (1 << MCID::Predicable); in isPredicable()
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/external/llvm/lib/Target/ARM/
DARMCodeEmitter.cpp101 const MCInstrDesc &MCID,
107 const MCInstrDesc &MCID) const;
275 const MCInstrDesc &MCID = MI.getDesc(); in getHiLo16ImmOpValue() local
278 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ? in getHiLo16ImmOpValue()
464 const MCInstrDesc &MCID = MI.getDesc(); in getMachineOpValue() local
466 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) in getMachineOpValue()
806 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelInstruction() local
814 Binary |= getAddrModeSBit(MI, MCID); in emitLEApcrelInstruction()
833 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelJTInstruction() local
842 Binary |= getAddrModeSBit(MI, MCID); in emitLEApcrelJTInstruction()
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DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
24 if (MCID.mayStore()) in hasRAWHazard()
26 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard()
46 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType() local
47 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
DThumb2SizeReduction.cpp188 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { in HasImplicitCPSRDef() argument
189 for (const unsigned *Regs = MCID.ImplicitDefs; *Regs; ++Regs) in HasImplicitCPSRDef()
500 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial() local
501 if (MCID.hasOptionalDef() && in ReduceSpecial()
502 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
524 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial() local
525 if (MCID.mayLoad() || MCID.mayStore()) in ReduceSpecial()
622 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr() local
623 if (MCID.hasOptionalDef()) { in ReduceTo2Addr()
624 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr()
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DMLxExpansionPass.cpp140 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
141 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
142 if (MCID.mayStore()) in hasRAWHazard()
144 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard()
276 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions() local
277 if (MCID.isBarrier()) { in ExpandFPMLxInstructions()
284 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in ExpandFPMLxInstructions()
294 if (!TII->isFpMLxInstruction(MCID.getOpcode(), in ExpandFPMLxInstructions()
/external/llvm/lib/Target/
DTargetInstrInfo.cpp31 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass() argument
33 if (OpNum >= MCID.getNumOperands()) in getRegClass()
36 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass()
37 if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) in getRegClass()
133 const MCInstrDesc &MCID = MI->getDesc(); in isUnpredicatedTerminator() local
134 if (!MCID.isTerminator()) return false; in isUnpredicatedTerminator()
137 if (MCID.isBranch() && !MCID.isBarrier()) in isUnpredicatedTerminator()
139 if (!MCID.isPredicable()) in isUnpredicatedTerminator()
/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h183 const MCInstrDesc &MCID) { in BuildMI() argument
184 return MachineInstrBuilder(MF.CreateMachineInstr(MCID, DL)); in BuildMI()
192 const MCInstrDesc &MCID, in BuildMI() argument
194 return MachineInstrBuilder(MF.CreateMachineInstr(MCID, DL)) in BuildMI()
205 const MCInstrDesc &MCID, in BuildMI() argument
207 MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL); in BuildMI()
219 const MCInstrDesc &MCID) { in BuildMI() argument
220 MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL); in BuildMI()
231 const MCInstrDesc &MCID) { in BuildMI() argument
232 return BuildMI(*BB, BB->end(), DL, MCID); in BuildMI()
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DMachineInstr.h60 const MCInstrDesc *MCID; // Instruction descriptor.
107 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
112 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
117 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
124 const MCInstrDesc &MCID);
195 const MCInstrDesc &getDesc() const { return *MCID; }
199 int getOpcode() const { return MCID->Opcode; }
512 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
/external/llvm/lib/CodeGen/
DMachineInstr.cpp467 : MCID(0), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), in MachineInstr()
475 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
476 for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs) in addImplicitDefUseOperands()
478 if (MCID->ImplicitUses) in addImplicitDefUseOperands()
479 for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses) in addImplicitDefUseOperands()
487 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), in MachineInstr()
490 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); in MachineInstr()
491 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); in MachineInstr()
501 : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), in MachineInstr()
504 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); in MachineInstr()
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DScoreboardHazardRecognizer.cpp118 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType() local
119 if (MCID == NULL) { in getHazardType()
123 unsigned idx = MCID->getSchedClass(); in getHazardType()
176 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
177 assert(MCID && "The scheduler must filter non-machineinstrs"); in EmitInstruction()
178 if (DAG->TII->isZeroCost(MCID->Opcode)) in EmitInstruction()
185 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
DTargetInstrInfoImpl.cpp62 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction() local
63 bool HasDef = MCID.getNumDefs(); in commuteInstruction()
122 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices() local
123 if (!MCID.isCommutable()) in findCommutedOpIndices()
127 SrcOpIdx1 = MCID.getNumDefs(); in findCommutedOpIndices()
140 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction() local
141 if (!MCID.isPredicable()) in PredicateInstruction()
145 if (MCID.OpInfo[i].isPredicate()) { in PredicateInstruction()
335 const MCInstrDesc &MCID = MI->getDesc(); in isReallyTriviallyReMaterializableGeneric() local
338 if (MCID.isNotDuplicable() || MCID.mayStore() || in isReallyTriviallyReMaterializableGeneric()
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DMachineVerifier.cpp544 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineInstrBefore() local
545 if (MI->getNumOperands() < MCID.getNumOperands()) { in visitMachineInstrBefore()
547 *OS << MCID.getNumOperands() << " operands expected, but " in visitMachineInstrBefore()
554 if ((*I)->isLoad() && !MCID.mayLoad()) in visitMachineInstrBefore()
556 if ((*I)->isStore() && !MCID.mayStore()) in visitMachineInstrBefore()
578 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineOperand() local
579 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; in visitMachineOperand()
582 if (MONum < MCID.getNumDefs()) { in visitMachineOperand()
589 } else if (MONum < MCID.getNumOperands()) { in visitMachineOperand()
593 !(MCID.isVariadic() && MONum == MCID.getNumOperands()-1)) { in visitMachineOperand()
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DPeepholeOptimizer.cpp356 const MCInstrDesc &MCID = MI->getDesc(); in isMoveImmediate() local
357 if (!MCID.isMoveImmediate()) in isMoveImmediate()
359 if (MCID.getNumDefs() != 1) in isMoveImmediate()
432 const MCInstrDesc &MCID = MI->getDesc(); in runOnMachineFunction() local
434 if (MCID.isBitcast()) { in runOnMachineFunction()
441 } else if (MCID.isCompare()) { in runOnMachineFunction()
DExpandISelPseudos.cpp65 const MCInstrDesc &MCID = MI->getDesc(); in runOnMachineFunction() local
66 if (MCID.usesCustomInsertionHook()) { in runOnMachineFunction()
DTwoAddressInstructionPass.cpp283 const MCInstrDesc &MCID = UseMI->getDesc(); in isTwoAddrUse() local
284 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { in isTwoAddrUse()
446 const MCInstrDesc &MCID = MI.getDesc(); in isTwoAddrUse() local
448 ? MI.getNumOperands() : MCID.getNumOperands(); in isTwoAddrUse()
765 const MCInstrDesc &MCID = MI->getDesc(); in isSafeToDelete() local
766 if (MCID.mayStore() || MCID.isCall()) in isSafeToDelete()
768 if (MCID.isTerminator() || MI->hasUnmodeledSideEffects()) in isSafeToDelete()
858 const MCInstrDesc &MCID = mi->getDesc(); in TryInstructionTransform() local
880 if (MCID.isCommutable() && mi->getNumOperands() >= 3 && in TryInstructionTransform()
911 if (MCID.isConvertibleTo3Addr()) { in TryInstructionTransform()
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DScheduleDAGInstrs.cpp240 const MCInstrDesc &MCID = MI->getDesc(); in BuildSchedGraph() local
241 assert(!MCID.isTerminator() && !MI->isLabel() && in BuildSchedGraph()
245 SU->isCall = MCID.isCall(); in BuildSchedGraph()
246 SU->isCommutable = MCID.isCommutable(); in BuildSchedGraph()
421 if (MCID.isCall() || MI->hasUnmodeledSideEffects() || in BuildSchedGraph()
423 (!MCID.mayLoad() || !MI->isInvariantLoad(AA)))) { in BuildSchedGraph()
462 } else if (MCID.mayStore()) { in BuildSchedGraph()
518 } else if (MCID.mayLoad()) { in BuildSchedGraph()
DMachineCSE.cpp263 const MCInstrDesc &MCID = MI->getDesc(); in isCSECandidate() local
264 if (MCID.mayStore() || MCID.isCall() || MCID.isTerminator() || in isCSECandidate()
268 if (MCID.mayLoad()) { in isCSECandidate()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassemblerCore.cpp593 const MCInstrDesc &MCID = ARMInsts[Opcode]; in DisassembleMulFrm() local
594 unsigned short NumDefs = MCID.getNumDefs(); in DisassembleMulFrm()
595 const MCOperandInfo *OpInfo = MCID.OpInfo; in DisassembleMulFrm()
744 const MCInstrDesc &MCID = ARMInsts[Opcode]; in DisassembleCoprocessor() local
746 (MCID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; in DisassembleCoprocessor()
981 const MCInstrDesc &MCID = ARMInsts[Opcode]; in DisassembleDPFrm() local
982 unsigned short NumDefs = MCID.getNumDefs(); in DisassembleDPFrm()
983 bool isUnary = isUnaryDP(MCID.TSFlags); in DisassembleDPFrm()
984 const MCOperandInfo *OpInfo = MCID.OpInfo; in DisassembleDPFrm()
1046 if (isUnary && (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)) { in DisassembleDPFrm()
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DThumbDisassemblerCore.h428 const MCInstrDesc &MCID = ARMInsts[Opcode]; in DisassembleThumb1DP() local
429 const MCOperandInfo *OpInfo = MCID.OpInfo; in DisassembleThumb1DP()
457 if ((Idx = MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO)) != -1) { in DisassembleThumb1DP()
514 const MCInstrDesc &MCID = ARMInsts[Opcode]; in DisassembleThumb1Special() local
515 const MCOperandInfo *OpInfo = MCID.OpInfo; in DisassembleThumb1Special()
533 if ((Idx = MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO)) != -1) { in DisassembleThumb1Special()
633 const MCInstrDesc &MCID = ARMInsts[Opcode]; in DisassembleThumb1LdSt() local
634 const MCOperandInfo *OpInfo = MCID.OpInfo; in DisassembleThumb1LdSt()
1426 const MCInstrDesc &MCID = ARMInsts[Opcode]; in DisassembleThumb2DPSoReg() local
1427 const MCOperandInfo *OpInfo = MCID.OpInfo; in DisassembleThumb2DPSoReg()
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/external/llvm/lib/Target/SystemZ/
DSystemZInstrBuilder.h111 const MCInstrDesc &MCID = MI->getDesc(); variable
113 if (MCID.mayLoad())
115 if (MCID.mayStore())
DSystemZInstrInfo.cpp206 const MCInstrDesc &MCID = MI->getDesc(); in isUnpredicatedTerminator() local
207 if (!MCID.isTerminator()) return false; in isUnpredicatedTerminator()
210 if (MCID.isBranch() && !MCID.isBarrier()) in isUnpredicatedTerminator()
212 if (!MCID.isPredicable()) in isUnpredicatedTerminator()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp252 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
253 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in CopyAndMoveSuccessors()
254 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
259 if (MCID.isCommutable()) in CopyAndMoveSuccessors()
425 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
426 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
427 unsigned NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
428 for (const unsigned *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
508 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
509 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
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/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp164 const MCInstrDesc &MCID = MI->getDesc(); in isUnpredicatedTerminator() local
165 if (!MCID.isTerminator()) return false; in isUnpredicatedTerminator()
168 if (MCID.isBranch() && !MCID.isBarrier()) in isUnpredicatedTerminator()
170 if (!MCID.isPredicable()) in isUnpredicatedTerminator()
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h153 const MCInstrDesc &MCID = MI->getDesc(); variable
155 if (MCID.mayLoad())
157 if (MCID.mayStore())
/external/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp76 const MCInstrDesc &MCID = TII.get(Opcode); in GetInstrType() local
78 isLoad = MCID.mayLoad(); in GetInstrType()
79 isStore = MCID.mayStore(); in GetInstrType()
81 uint64_t TSFlags = MCID.TSFlags; in GetInstrType()

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