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Searched refs:MCInstrDesc (Results 1 – 25 of 71) sorted by relevance

123

/external/llvm/include/llvm/MC/
DMCInstrInfo.h27 const MCInstrDesc *Desc; // Raw array to allow static init'n
33 void InitMCInstrInfo(const MCInstrDesc *D, unsigned NO) { in InitMCInstrInfo()
43 const MCInstrDesc &get(unsigned Opcode) const { in get()
/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h25 class MCInstrDesc; variable
183 const MCInstrDesc &MCID) { in BuildMI()
192 const MCInstrDesc &MCID, in BuildMI()
205 const MCInstrDesc &MCID, in BuildMI()
219 const MCInstrDesc &MCID) { in BuildMI()
231 const MCInstrDesc &MCID) { in BuildMI()
241 const MCInstrDesc &MCID, in BuildMI()
DMachineInstr.h60 const MCInstrDesc *MCID; // Instruction descriptor.
107 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
112 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
117 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
124 const MCInstrDesc &MCID);
195 const MCInstrDesc &getDesc() const { return *MCID; }
512 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.h25 class MCInstrDesc; variable
52 const MCInstrDesc &II,
66 const MCInstrDesc *II,
76 const MCInstrDesc *II,
DInstrEmitter.cpp109 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); in EmitCopyFromReg()
181 const MCInstrDesc &II, in CreateVirtualRegisters()
268 const MCInstrDesc *II, in AddRegisterOperand()
278 const MCInstrDesc &MCID = MI->getDesc(); in AddRegisterOperand()
333 const MCInstrDesc *II, in AddOperand()
559 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
600 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgValue()
671 const MCInstrDesc &II = TII->get(Opc); in EmitMachineNode()
700 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); in EmitMachineNode()
DFastISel.cpp550 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); in SelectCall()
1093 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_()
1103 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_r()
1123 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rr()
1145 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rrr()
1168 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_ri()
1189 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rii()
1212 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rf()
1234 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rri()
1256 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_i()
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.h100 const MCInstrDesc& getBrCond(SystemZCC::CondCodes CC) const;
101 const MCInstrDesc& getLongDispOpc(unsigned Opc) const;
103 const MCInstrDesc& getMemoryInstr(unsigned Opc, int64_t Offset = 0) const {
/external/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
46 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
49 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
DARMBaseInstrInfo.h351 const MCInstrDesc &DefMCID,
355 const MCInstrDesc &DefMCID,
359 const MCInstrDesc &UseMCID,
363 const MCInstrDesc &UseMCID,
367 const MCInstrDesc &DefMCID,
369 const MCInstrDesc &UseMCID,
DARMCodeEmitter.cpp101 const MCInstrDesc &MCID,
107 const MCInstrDesc &MCID) const;
275 const MCInstrDesc &MCID = MI.getDesc(); in getHiLo16ImmOpValue()
464 const MCInstrDesc &MCID = MI.getDesc(); in getMachineOpValue()
806 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelInstruction()
833 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelJTInstruction()
1002 const MCInstrDesc &MCID, in getMachineSoRegOpValue()
1072 const MCInstrDesc &MCID) const { in getAddrModeSBit()
1084 const MCInstrDesc &MCID = MI.getDesc(); in emitDataProcessingInstruction()
1187 const MCInstrDesc &MCID = MI.getDesc(); in emitLoadStoreInstruction()
[all …]
DMLxExpansionPass.cpp140 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
221 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
222 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
276 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions()
DThumb2SizeReduction.cpp188 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { in HasImplicitCPSRDef()
500 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial()
524 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial()
608 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2); in ReduceTo2Addr()
622 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr()
680 const MCInstrDesc &MCID = MI->getDesc(); in ReduceToNarrow()
699 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1); in ReduceToNarrow()
DARMBaseInstrInfo.cpp143 const MCInstrDesc &MCID = MI->getDesc(); in convertToThreeAddress()
482 const MCInstrDesc &MCID = MI->getDesc(); in DefinesPredicate()
502 const MCInstrDesc &MCID = MI->getDesc(); in isPredicable()
531 const MCInstrDesc &MCID = MI->getDesc(); in GetInstSizeInBytes()
1365 const MCInstrDesc &Desc = MI.getDesc(); in rewriteARMFrameIndex()
1805 const MCInstrDesc &Desc = MI->getDesc(); in getNumMicroOps()
1908 const MCInstrDesc &DefMCID, in getVLDMDefCycle()
1949 const MCInstrDesc &DefMCID, in getLDMDefCycle()
1984 const MCInstrDesc &UseMCID, in getVSTMUseCycle()
2024 const MCInstrDesc &UseMCID, in getSTMUseCycle()
[all …]
DThumb1RegisterInfo.cpp241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); in emitThumbRegPlusImmediate()
293 const MCInstrDesc &MCID = TII.get(ExtraOpc); in emitThumbRegPlusImmediate()
362 const MCInstrDesc &MCID = TII.get(ARM::tRSB); in emitThumbConstant()
396 const MCInstrDesc &Desc = MI.getDesc(); in rewriteFrameIndex()
653 const MCInstrDesc &Desc = MI.getDesc(); in eliminateFrameIndex()
/external/llvm/lib/Target/Mips/
DMipsExpandPseudo.cpp64 const MCInstrDesc& MCid = I->getDesc(); in runOnMachineBasicBlock()
90 const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1); in ExpandBuildPairF64()
106 const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1); in ExpandExtractElementF64()
DMipsDelaySlotFiller.cpp62 const MCInstrDesc& MCid = I->getDesc(); in runOnMachineBasicBlock()
/external/llvm/lib/Target/MBlaze/
DMBlazeDelaySlotFiller.cpp112 MCInstrDesc desc = candidate->getDesc(); in delayHasHazard()
186 MCInstrDesc brdesc = (--candidate)->getDesc(); in isDelayFiller()
214 MCInstrDesc desc = I->getDesc(); in findDelayInstr()
/external/llvm/lib/Target/PTX/
DPTXInstrInfo.cpp52 const MCInstrDesc &MCID = get(map[i].opcode); in copyPhysReg()
74 const MCInstrDesc &MCID = get(map[i].opcode); in copyRegToReg()
183 const MCInstrDesc &desc1 = instLast1.getDesc(); in AnalyzeBranch()
189 const MCInstrDesc &desc2 = IsSizeOne ? desc1 : instLast2.getDesc(); in AnalyzeBranch()
392 const MCInstrDesc &desc = inst.getDesc(); in IsAnyKindOfBranch()
/external/llvm/lib/Target/
DTargetInstrInfo.cpp31 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass()
133 const MCInstrDesc &MCID = MI->getDesc(); in isUnpredicatedTerminator()
/external/llvm/lib/CodeGen/
DTargetInstrInfoImpl.cpp62 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction()
122 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices()
140 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction()
335 const MCInstrDesc &MCID = MI->getDesc(); in isReallyTriviallyReMaterializableGeneric()
DScoreboardHazardRecognizer.cpp118 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType()
176 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
DExpandISelPseudos.cpp65 const MCInstrDesc &MCID = MI->getDesc(); in runOnMachineFunction()
DMachineInstr.cpp486 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp) in MachineInstr()
499 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl, in MachineInstr()
515 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid) in MachineInstr()
530 const MCInstrDesc &tid) in MachineInstr()
944 const MCInstrDesc &MCID = getDesc(); in findFirstPredOperandIdx()
1003 const MCInstrDesc &MCID = getDesc(); in isRegTiedToUseOperand()
1063 const MCInstrDesc &MCID = getDesc(); in isRegTiedToDefOperand()
1109 const MCInstrDesc &MCID = MI->getDesc(); in copyPredicates()
/external/llvm/lib/Target/Blackfin/
DBlackfinISelDAGToDAG.cpp149 const MCInstrDesc &DefMCID = TII.get(NI->getMachineOpcode()); in FixRegisterClasses()
159 const MCInstrDesc &UseMCID = TII.get(UI->getMachineOpcode()); in FixRegisterClasses()
/external/llvm/lib/Target/X86/
DX86MCCodeEmitter.cpp120 const MCInst &MI, const MCInstrDesc &Desc,
128 const MCInst &MI, const MCInstrDesc &Desc,
382 const MCInstrDesc &Desc, in EmitVEXOpcodePrefix()
589 const MCInstrDesc &Desc) { in DetermineREXPrefix()
716 const MCInstrDesc &Desc, in EmitOpcodePrefix()
806 const MCInstrDesc &Desc = MCII.get(Opcode); in EncodeInstruction()

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