| /external/llvm/lib/Target/CellSPU/ |
| D | SPUISelDAGToDAG.cpp | 231 SDNode *SelectSHLi64(SDNode *N, EVT OpVT);
234 SDNode *SelectSRLi64(SDNode *N, EVT OpVT);
237 SDNode *SelectSRAi64(SDNode *N, EVT OpVT);
240 SDNode *SelectI64Constant(SDNode *N, EVT OpVT, DebugLoc dl);
243 SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
620 EVT OpVT = N->getValueType(0); in Select() local
645 } else if (Opc == ISD::Constant && OpVT == MVT::i64) { in Select()
649 return SelectI64Constant(N, OpVT, N->getDebugLoc()); in Select()
651 && OpVT == MVT::i64) { in Select()
657 OpVT, (128 / OpVT.getSizeInBits())); in Select()
[all …]
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| D | SPUISelLowering.cpp | 1717 SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal, in LowerV2I64Splat() argument
1725 return DAG.getNode(ISD::BITCAST, dl, OpVT, in LowerV2I64Splat()
1754 LO32 = DAG.getNode(ISD::BITCAST, dl, OpVT, in LowerV2I64Splat()
1762 HI32 = DAG.getNode(ISD::BITCAST, dl, OpVT, in LowerV2I64Splat()
1800 return DAG.getNode(SPUISD::SHUFB, dl, OpVT, HI32, LO32, in LowerV2I64Splat()
2457 EVT OpVT = Op.getValueType(); in LowerFP_TO_INT() local
2461 if ((OpVT == MVT::i32 && Op0VT == MVT::f64) in LowerFP_TO_INT()
2462 || OpVT == MVT::i64) { in LowerFP_TO_INT()
2466 ? RTLIB::getFPTOSINT(Op0VT, OpVT) in LowerFP_TO_INT()
2467 : RTLIB::getFPTOUINT(Op0VT, OpVT); in LowerFP_TO_INT()
[all …]
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| D | SPUISelLowering.h | 80 SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat,
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| /external/llvm/include/llvm/CodeGen/ |
| D | RuntimeLibcalls.h | 306 Libcall getFPEXT(EVT OpVT, EVT RetVT);
310 Libcall getFPROUND(EVT OpVT, EVT RetVT);
314 Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
318 Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
322 Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
326 Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 338 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { in getFPEXT() argument
339 if (OpVT == MVT::f32) { in getFPEXT()
349 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { in getFPROUND() argument
351 if (OpVT == MVT::f64) in getFPROUND()
353 if (OpVT == MVT::f80) in getFPROUND()
355 if (OpVT == MVT::ppcf128) in getFPROUND()
358 if (OpVT == MVT::f80) in getFPROUND()
360 if (OpVT == MVT::ppcf128) in getFPROUND()
369 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { in getFPTOSINT() argument
370 if (OpVT == MVT::f32) { in getFPTOSINT()
[all …]
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| D | ScheduleDAGSDNodes.cpp | 424 EVT OpVT = N->getOperand(i).getValueType(); in AddSchedEdges() local
425 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!"); in AddSchedEdges()
426 bool isChain = OpVT == MVT::Other; in AddSchedEdges()
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| D | LegalizeTypes.cpp | 276 EVT OpVT = N->getOperand(i).getValueType(); in run() local
277 switch (getTypeAction(OpVT)) { in run()
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| D | LegalizeDAG.cpp | 828 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); in LegalizeOp() local
831 Action = TLI.getCondCodeAction(CCCode, OpVT); in LegalizeOp()
837 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); in LegalizeOp()
1944 EVT OpVT = LHS.getValueType(); in LegalizeSetCCCondCode() local
1946 switch (TLI.getCondCodeAction(CCCode, OpVT)) { in LegalizeSetCCCondCode()
2055 EVT OpVT = Node->getOperand(0).getValueType(); in ExpandBUILD_VECTOR() local
2097 if (OpVT==EltVT) in ExpandBUILD_VECTOR()
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| D | DAGCombiner.cpp | 5465 EVT OpVT = N0.getValueType(); in visitSINT_TO_FP() local
5468 if (N0C && OpVT != MVT::ppcf128 && in visitSINT_TO_FP()
5476 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && in visitSINT_TO_FP()
5477 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { in visitSINT_TO_FP()
5490 EVT OpVT = N0.getValueType(); in visitUINT_TO_FP() local
5493 if (N0C && OpVT != MVT::ppcf128 && in visitUINT_TO_FP()
5501 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && in visitUINT_TO_FP()
5502 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { in visitUINT_TO_FP()
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| D | SelectionDAGBuilder.cpp | 5627 EVT OpVT = MVT::Other; in visitInlineAsm() local
5643 OpVT = TLI.getValueType(STy->getElementType(ResNo)); in visitInlineAsm()
5646 OpVT = TLI.getValueType(CS.getType()); in visitInlineAsm()
5667 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); in visitInlineAsm()
5670 OpInfo.ConstraintVT = OpVT; in visitInlineAsm()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 5246 static SDValue getVZextMovL(EVT VT, EVT OpVT, in getVZextMovL() argument
5256 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; in getVZextMovL()
5262 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; in getVZextMovL()
5264 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, in getVZextMovL()
5266 OpVT, in getVZextMovL()
5274 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, in getVZextMovL()
5276 OpVT, SrcOp))); in getVZextMovL()
6259 EVT OpVT = Op.getValueType(); in LowerSCALAR_TO_VECTOR() local
6263 if (OpVT.getSizeInBits() > 128) { in LowerSCALAR_TO_VECTOR()
6266 OpVT.getVectorElementType(), in LowerSCALAR_TO_VECTOR()
[all …]
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| D | X86InstrSSE.td | 2246 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2253 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2259 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
4694 ValueType OpVT, bit Is2Addr = 1> {
4701 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3059 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; in LowerFCOPYSIGN() local
3061 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, in LowerFCOPYSIGN()
3062 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), in LowerFCOPYSIGN()
3069 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, in LowerFCOPYSIGN()
3070 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
3076 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
3077 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); in LowerFCOPYSIGN()
3082 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, in LowerFCOPYSIGN()
3083 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); in LowerFCOPYSIGN()
3085 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, in LowerFCOPYSIGN()
[all …]
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| /external/llvm/utils/TableGen/ |
| D | CodeGenDAGPatterns.cpp | 1499 MVT::SimpleValueType OpVT = Int->IS.ParamVTs[i]; in ApplyTypeConstraints() local
1501 MadeChange |= getChild(i+1)->UpdateNodeType(0, OpVT, TP); in ApplyTypeConstraints()
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