| /external/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 88 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in CheckReturn() argument
91 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { in CheckReturn()
92 MVT VT = Outs[i].VT; in CheckReturn()
93 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in CheckReturn()
102 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn() argument
105 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { in AnalyzeReturn()
106 MVT VT = Outs[i].VT; in AnalyzeReturn()
107 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in AnalyzeReturn()
120 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands() argument
122 unsigned NumOps = Outs.size(); in AnalyzeCallOperands()
[all …]
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.h | 97 const SmallVectorImpl<ISD::OutputArg> &Outs,
126 const SmallVectorImpl<ISD::OutputArg> &Outs,
135 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| D | SystemZISelLowering.cpp | 257 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCall() argument
271 Outs, OutVals, Ins, dl, DAG, InVals); in LowerCall()
376 &Outs, in LowerCCCCallTo() argument
392 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ); in LowerCCCCallTo()
555 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
567 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ); in LowerReturn()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 128 const SmallVectorImpl<ISD::OutputArg> &Outs,
157 const SmallVectorImpl<ISD::OutputArg> &Outs,
166 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| D | MSP430ISelLowering.cpp | 274 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCall() argument
288 Outs, OutVals, Ins, dl, DAG, InVals); in LowerCall()
384 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
392 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) { in LowerReturn()
402 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430); in LowerReturn()
445 &Outs, in LowerCCCCallTo() argument
455 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430); in LowerCCCCallTo()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.h | 83 const SmallVectorImpl<ISD::OutputArg> &Outs,
92 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| D | SparcISelLowering.cpp | 83 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
97 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); in LowerReturn()
352 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCall() argument
364 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); in LowerCall()
376 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { in LowerCall()
377 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall()
410 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; in LowerCall()
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| /external/llvm/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.h | 68 const SmallVectorImpl<ISD::OutputArg> &Outs,
77 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| D | BlackfinISelLowering.cpp | 224 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
236 CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin); in LowerReturn()
283 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCall() argument
296 CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin); in LowerCall()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.h | 120 const SmallVectorImpl<ISD::OutputArg> &Outs,
180 const SmallVectorImpl<ISD::OutputArg> &Outs,
189 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| D | XCoreISelLowering.cpp | 864 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCall() argument
880 Outs, OutVals, Ins, dl, DAG, InVals); in LowerCall()
892 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCCCCallTo() argument
907 CCInfo.AnalyzeCallOperands(Outs, CC_XCore); in LowerCCCCallTo()
1190 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn() argument
1194 return CCInfo.CheckReturn(Outs, RetCC_XCore); in CanLowerReturn()
1200 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
1213 CCInfo.AnalyzeReturn(Outs, RetCC_XCore); in LowerReturn()
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| /external/llvm/lib/Target/Alpha/ |
| D | AlphaISelLowering.h | 127 const SmallVectorImpl<ISD::OutputArg> &Outs,
136 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| D | AlphaISelLowering.cpp | 226 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCall() argument
239 CCInfo.AnalyzeCallOperands(Outs, CC_Alpha); in LowerCall()
472 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
480 switch (Outs.size()) { in LowerReturn()
487 EVT ArgVT = Outs[0].VT; in LowerReturn()
502 EVT ArgVT = Outs[0].VT; in LowerReturn()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 441 const SmallVectorImpl<ISD::OutputArg> &Outs,
450 const SmallVectorImpl<ISD::OutputArg> &Outs,
470 const SmallVectorImpl<ISD::OutputArg> &Outs,
478 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.h | 138 const SmallVectorImpl<ISD::OutputArg> &Outs,
147 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUISelLowering.h | 166 const SmallVectorImpl<ISD::OutputArg> &Outs,
175 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 146 const SmallVectorImpl<ISD::OutputArg> &Outs,
155 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/Target/PTX/ |
| D | PTXISelLowering.cpp | 291 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
301 assert(Outs.size() == 0 && "Kernel must return void."); in LowerReturn()
321 CCInfo.AnalyzeReturn(Outs, RetCC_PTX); in LowerReturn()
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| D | PTXISelLowering.h | 58 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 441 const SmallVectorImpl<ISD::OutputArg> &Outs,
458 const SmallVectorImpl<ISD::OutputArg> &Outs,
465 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 201 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
212 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 753 const SmallVectorImpl<ISD::OutputArg> &Outs,
842 const SmallVectorImpl<ISD::OutputArg> &Outs,
851 const SmallVectorImpl<ISD::OutputArg> &Outs,
866 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| D | X86FastISel.cpp | 704 SmallVector<ISD::OutputArg, 4> Outs; in X86SelectRet() local
706 Outs, TLI); in X86SelectRet()
712 CCInfo.AnalyzeReturn(Outs, RetCC_X86); in X86SelectRet()
745 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
751 if (Outs[0].Flags.isSExt()) in X86SelectRet()
756 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : in X86SelectRet()
1502 SmallVector<ISD::OutputArg, 4> Outs; in DoSelectCall() local
1505 Outs, TLI, &Offsets); in DoSelectCall()
1508 Outs, FTy->getContext()); in DoSelectCall()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 67 SmallVector<ISD::OutputArg, 4> Outs; in set() local
69 Fn->getAttributes().getRetAttributes(), Outs, TLI); in set()
72 Outs, Fn->getContext()); in set()
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 1195 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCall() argument
1213 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn() argument
1227 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
1964 SmallVectorImpl<ISD::OutputArg> &Outs,
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