Searched refs:PPCSubTarget (Results 1 – 4 of 4) sorted by relevance
68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { in PPCTargetLowering()401 if (PPCSubTarget.isDarwin()) in PPCTargetLowering()901 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, in SelectAddressRegImm()950 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, in SelectAddressRegRegOnly()1016 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, in SelectAddressRegImmShift()1199 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { in LowerGlobalAddress()1604 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { in LowerFormalArguments()2434 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()2528 const PPCSubtarget &PPCSubTarget) { in PrepareCall() argument2530 bool isPPC64 = PPCSubTarget.isPPC64(); in PrepareCall()[all …]
44 const PPCSubtarget &PPCSubTarget; member in __anon430f72250111::PPCDAGToDAGISel50 PPCSubTarget(*TM.getSubtargetImpl()) {} in PPCDAGToDAGISel()702 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1) in SelectSETCC()838 if (PPCSubTarget.isGigaProcessor()) in Select()
237 const PPCSubtarget &PPCSubTarget; variable
353 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;354 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;