| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 103 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
104 ; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
106 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
111 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
134 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
135 ; CHECK: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
137 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
142 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
165 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
166 ; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 67 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, in getCalleeSavedRegs()
79 ARM::R11, ARM::R10, ARM::R8, in getCalleeSavedRegs()
409 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, in getRawAllocationOrder()
416 ARM::R8, ARM::R10 in getRawAllocationOrder()
421 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, in getRawAllocationOrder()
428 ARM::R8, ARM::R10 in getRawAllocationOrder()
434 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, in getRawAllocationOrder()
439 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, in getRawAllocationOrder()
445 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, in getRawAllocationOrder()
452 ARM::R10 in getRawAllocationOrder()
[all …]
|
| D | ARMBaseRegisterInfo.h | 58 case R8: case R9: case R10: case R11: in isARMArea1Register()
69 case R8: case R9: case R10: case R11: in isARMArea2Register()
|
| D | ARMBaseInfo.h | 168 case R10: case S10: case D10: case Q10: return 10; in getARMRegisterNumbering()
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreFrameLowering.cpp | 172 storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl, TII); in emitPrologue()
174 MBB.addLiveIn(XCore::R10); in emitPrologue()
179 MachineLocation CSSrc(XCore::R10); in emitPrologue()
183 unsigned FramePtr = XCore::R10; in emitPrologue()
224 unsigned FramePtr = XCore::R10; in emitEpilogue()
250 loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl, TII); in emitEpilogue()
|
| D | XCoreRegisterInfo.td | 36 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
51 R4, R5, R6, R7, R8, R9, R10)>;
|
| D | XCoreRegisterInfo.cpp | 80 XCore::R8, XCore::R9, XCore::R10, XCore::LR, in getCalleeSavedRegs()
95 Reserved.set(XCore::R10); in getReservedRegs()
326 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP; in getFrameRegister()
|
| /external/llvm/test/CodeGen/Blackfin/ |
| D | jumptable.ll | 49 %R10 = xor i32 %A, %B ; <i32> [#uses=1]
50 ret i32 %R10
|
| /external/llvm/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 25 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
42 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
|
| D | SPURegisterInfo.cpp | 64 case SPU::R10: return 10; in getRegisterNumbering()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 25 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
42 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
75 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
|
| D | PPCRegisterInfo.td | 78 def R10 : GPR<10, "r10">, DwarfRegNum<[-2, 10]>;
112 def X10 : GP8<R10, "r10">, DwarfRegNum<[10, -2]>;
|
| /external/kernel-headers/original/asm-x86/ |
| D | ptrace-abi.h | 36 #define R10 56 macro
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrControl.td | 215 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
247 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
267 // __chkstk(MSVC): clobber R10, R11 and EFLAGS.
268 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
269 let Defs = [RAX, R10, R11, RSP, EFLAGS],
280 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
|
| D | X86RegisterInfo.cpp | 99 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: in getSEHRegNum()
409 X86::R8, X86::R9, X86::R10, X86::R11, in getReservedRegs()
678 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegister()
715 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegister()
751 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegister()
787 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegister()
788 return X86::R10; in getX86SubSuperRegister()
|
| D | X86CallingConv.td | 143 // The 'nest' parameter, if any, is passed in R10.
144 CCIfNest<CCAssignToReg<[R10]>>,
190 // The 'nest' parameter, if any, is passed in R10.
191 CCIfNest<CCAssignToReg<[R10]>>,
|
| /external/llvm/lib/Target/Alpha/ |
| D | AlphaRegisterInfo.td | 48 def R10 : GPR<10, "$10">, DwarfRegNum<[10]>;
122 R9, R10, R11, R12, R13, R14,
|
| D | AlphaRegisterInfo.cpp | 60 Alpha::R9, Alpha::R10, in getCalleeSavedRegs()
|
| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.cpp | 62 case MBlaze::R10 : return 10; in getRegisterNumbering()
127 case 10 : return MBlaze::R10; in getRegisterFromNumbering()
|
| D | MBlazeRegisterInfo.td | 52 def R10 : MBlazeGPRReg< 10, "r10">, DwarfRegNum<[10]>;
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| D | sigframe-arm-linux.c | 137 SC2(r10,R10); in synth_ucontext()
310 REST(r10,R10); in VG_()
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 171 ENTRY(R10) \
189 ENTRY(R10) \
|
| /external/valgrind/main/VEX/auxprogs/ |
| D | genoffsets.c | 109 GENOFFSET(AMD64,amd64,R10); in foo()
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 146 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: in getX86RegNum()
223 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: in InitLLVM2SEHRegisterMapping()
|
| /external/llvm/lib/Target/PTX/ |
| D | PTXCallingConv.td | 27 CCIfType<[i32,f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11]>>,
|