| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 105 ; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
107 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
136 ; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
138 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
168 ; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
170 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
229 ; CHECK: ll $[[R12:[0-9]+]], 0($[[R2]])
230 ; CHECK: and $[[R13:[0-9]+]], $[[R12]], $[[R6]]
233 ; CHECK: and $[[R14:[0-9]+]], $[[R12]], $[[R7]]
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | 2010-03-09-indirect-call.ll | 5 ; Indirect calls must use R12 on Darwin (i.e., R12 must contain the address of
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| /external/llvm/test/CodeGen/ARM/ |
| D | unaligned_load_store.ll | 13 ; GENERIC: ldrb [[R12:r[0-9]+]]
16 ; GENERIC: strb [[R12]]
|
| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 83 case X86::ECX: case X86::R12: return 2; in getCompactUnwindRegNum()
101 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: in getSEHRegNum()
338 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCalleeSavedRegs()
342 X86::RAX, X86::RDX, X86::RBX, X86::R12, in getCalleeSavedRegs()
348 X86::R12, X86::R13, X86::R14, X86::R15, in getCalleeSavedRegs()
410 X86::R12, X86::R13, X86::R14, X86::R15 in getReservedRegs()
682 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegister()
719 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegister()
755 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegister()
791 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegister()
[all …]
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| D | X86RegisterInfo.td | 139 def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
278 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
281 // Allocate R12 and R13 last, as these require an extra byte when
314 RBX, R14, R15, R12, R13, RBP, RSP, RIP)> {
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 410 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, in getRawAllocationOrder()
415 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, in getRawAllocationOrder()
422 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, in getRawAllocationOrder()
427 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, in getRawAllocationOrder()
434 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, in getRawAllocationOrder()
439 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, in getRawAllocationOrder()
446 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, in getRawAllocationOrder()
451 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, in getRawAllocationOrder()
458 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, in getRawAllocationOrder()
463 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, in getRawAllocationOrder()
[all …]
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| D | ARMBaseInfo.h | 170 case R12: case S12: case D12: case Q12: return 12; in getARMRegisterNumbering()
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| D | Thumb1RegisterInfo.cpp | 567 .addReg(ARM::R12, RegState::Define) in saveScavengerRegister()
583 if (MO.getReg() == ARM::R12) { in saveScavengerRegister()
592 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill)); in saveScavengerRegister()
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| /external/llvm/test/CodeGen/Thumb2/ |
| D | 2010-08-10-VarSizedAllocaBug.ll | 10 ; CHECK: sub.w [[R12:r[0-9]+]], r4, #1000
11 ; CHECK: mov sp, [[R12]]
|
| /external/llvm/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 26 R12, R13, R14, R15, R16, R17, R18, R19, R20,
43 R12, R13, R14, R15, R16, R17, R18, R19, R20,
|
| /external/kernel-headers/original/asm-x86/ |
| D | ptrace-abi.h | 31 #define R12 24 macro
|
| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineAndOrXor.cpp | 598 Value *R11,*R12; in foldLogOpOfMaskedICmpsHelper() local
600 if (match(R1, m_And(m_Value(R11), m_Value(R12)))) { in foldLogOpOfMaskedICmpsHelper()
602 A = R11; D = R12; E = R2; ok = true; in foldLogOpOfMaskedICmpsHelper()
605 if (R12 != 0 && (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22)) { in foldLogOpOfMaskedICmpsHelper()
606 A = R12; D = R11; E = R2; ok = true; in foldLogOpOfMaskedICmpsHelper()
609 if (!ok && match(R2, m_And(m_Value(R11), m_Value(R12)))) { in foldLogOpOfMaskedICmpsHelper()
611 A = R11; D = R12; E = R1; ok = true; in foldLogOpOfMaskedICmpsHelper()
614 if (R12 != 0 && (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22)) { in foldLogOpOfMaskedICmpsHelper()
615 A = R12; D = R11; E = R1; ok = true; in foldLogOpOfMaskedICmpsHelper()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 19 // i16 are returned in registers R15, R14, R13, R12
|
| /external/llvm/lib/Target/Alpha/ |
| D | AlphaRegisterInfo.td | 50 def R12 : GPR<12, "$12">, DwarfRegNum<[12]>;
122 R9, R10, R11, R12, R13, R14,
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| D | AlphaRegisterInfo.cpp | 61 Alpha::R11, Alpha::R12, in getCalleeSavedRegs()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.cpp | 64 case MBlaze::R12 : return 12; in getRegisterNumbering()
129 case 12 : return MBlaze::R12; in getRegisterFromNumbering()
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| D | MBlazeFrameLowering.cpp | 251 for (unsigned r = MBlaze::R3; r <= MBlaze::R12; ++r) { in interruptFrameLayout()
293 for (unsigned r = MBlaze::R12, i = VFI.size(); r >= MBlaze::R3; --r) { in interruptFrameLayout()
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| D | MBlazeRegisterInfo.td | 54 def R12 : MBlazeGPRReg< 12, "r12">, DwarfRegNum<[12]>;
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| D | sigframe-arm-linux.c | 139 SC2(ip,R12); in synth_ucontext()
312 REST(ip,R12); in VG_()
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 173 ENTRY(R12) \
191 ENTRY(R12) \
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmLexer.cpp | 137 .Case("ip", ARM::R12) in LexTokenUAL()
|
| /external/valgrind/main/VEX/auxprogs/ |
| D | genoffsets.c | 111 GENOFFSET(AMD64,amd64,R12); in foo()
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 150 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: in getX86RegNum()
225 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: in InitLLVM2SEHRegisterMapping()
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| /external/llvm/test/CodeGen/X86/ |
| D | ghc-cc64.ll | 7 @hp = external global i64 ; assigned to register: R12
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| /external/llvm/lib/Target/PTX/ |
| D | PTXCallingConv.td | 19 …CCIfType<[i32,f32], CCAssignToReg<[R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24…
|