| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 106 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
107 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
137 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
138 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
169 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
170 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
198 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
199 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R9]]
230 ; CHECK: and $[[R13:[0-9]+]], $[[R12]], $[[R6]]
231 ; CHECK: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]]
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 84 case X86::EDX: case X86::R13: return 3; in getCompactUnwindRegNum()
102 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: in getSEHRegNum()
338 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCalleeSavedRegs()
343 X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCalleeSavedRegs()
348 X86::R12, X86::R13, X86::R14, X86::R15, in getCalleeSavedRegs()
410 X86::R12, X86::R13, X86::R14, X86::R15 in getReservedRegs()
684 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegister()
721 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegister()
757 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegister()
793 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegister()
[all …]
|
| D | X86RegisterInfo.td | 140 def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
278 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
281 // Allocate R12 and R13 last, as these require an extra byte when
314 RBX, R14, R15, R12, R13, RBP, RSP, RIP)> {
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| D | X86CallingConv.td | 232 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
|
| /external/valgrind/main/VEX/auxprogs/ |
| D | genoffsets.c | 112 GENOFFSET(AMD64,amd64,R13); in foo()
155 GENOFFSET(ARM,arm,R13); in foo()
|
| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.cpp | 65 case MBlaze::R13 : return 13; in getRegisterNumbering()
130 case 13 : return MBlaze::R13; in getRegisterFromNumbering()
233 Reserved.set(MBlaze::R13); in getReservedRegs()
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| D | MBlazeRegisterInfo.td | 55 def R13 : MBlazeGPRReg< 13, "r13">, DwarfRegNum<[13]>;
|
| /external/llvm/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 26 R12, R13, R14, R15, R16, R17, R18, R19, R20,
43 R12, R13, R14, R15, R16, R17, R18, R19, R20,
|
| D | SPURegisterInfo.cpp | 67 case SPU::R13: return 13; in getRegisterNumbering()
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| D | SPURegisterInfo.td | 37 def R13 : SPUVecReg<13, "$13">, DwarfRegNum<[13]>;
|
| /external/kernel-headers/original/asm-x86/ |
| D | ptrace-abi.h | 30 #define R13 16 macro
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 19 // i16 are returned in registers R15, R14, R13, R12
|
| /external/llvm/lib/Target/Alpha/ |
| D | AlphaRegisterInfo.td | 51 def R13 : GPR<13, "$13">, DwarfRegNum<[13]>;
122 R9, R10, R11, R12, R13, R14,
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| D | AlphaRegisterInfo.cpp | 62 Alpha::R13, Alpha::R14, in getCalleeSavedRegs()
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| D | sigframe-arm-linux.c | 140 SC2(sp,R13); in synth_ucontext()
313 REST(sp,R13); in VG_()
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| D | sigframe-amd64-linux.c | 349 SC2(r13,R13); in synth_ucontext()
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 174 ENTRY(R13) \
192 ENTRY(R13) \
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 89 case R13: case X13: case F13: case V13: case CR3GT: return 13; in getRegisterNumbering()
149 PPC::R13, PPC::R14, PPC::R15, in getCalleeSavedRegs()
277 Reserved.set(PPC::R13); // Small Data Area pointer register in getReservedRegs()
290 Reserved.set(PPC::R13); in getReservedRegs()
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| D | PPCRegisterInfo.td | 81 def R13 : GPR<13, "r13">, DwarfRegNum<[-2, 13]>;
115 def X13 : GP8<R13, "r13">, DwarfRegNum<[13, -2]>;
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 152 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: in getX86RegNum()
226 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: in InitLLVM2SEHRegisterMapping()
|
| /external/llvm/test/CodeGen/X86/ |
| D | ghc-cc64.ll | 5 @base = external global i64 ; assigned to register: R13
|
| /external/llvm/lib/Target/PTX/ |
| D | PTXCallingConv.td | 19 …CCIfType<[i32,f32], CCAssignToReg<[R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24…
|
| /external/v8/src/ |
| D | platform-linux.cc | 832 enum ArmRegisters {R15 = 15, R13 = 13, R11 = 11}; enumerator
884 sample->sp = reinterpret_cast<Address>(mcontext.gregs[R13]); in ProfilerSignalHandler()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 220 // or SP (R13 or R15) are used. The ARM ISA refers to these operands
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| /external/valgrind/main/memcheck/ |
| D | mc_machine.c | 483 if (o == GOF(R13) && is1248) return o; in get_otrack_shadow_offset_wrk()
712 if (o == GOF(R13) && sz == 4) return o; in get_otrack_shadow_offset_wrk()
|