| /external/llvm/lib/Target/Alpha/ |
| D | AlphaFrameLowering.cpp | 96 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); in emitPrologue()
98 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15) in emitPrologue()
123 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) in emitEpilogue()
124 .addReg(Alpha::R15); in emitEpilogue()
126 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15) in emitEpilogue()
127 .addImm(0).addReg(Alpha::R15); in emitEpilogue()
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| D | AlphaRegisterInfo.cpp | 73 Reserved.set(Alpha::R15); in getReservedRegs()
149 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false); in eliminateFrameIndex()
172 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); in eliminateFrameIndex()
182 return TFI->hasFP(MF) ? Alpha::R15 : Alpha::R30; in getFrameRegister()
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| D | AlphaRegisterInfo.td | 53 def R15 : GPR<15, "$15">, DwarfRegNum<[15]>;
124 R15, R30, R31)>; //zero
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| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 111 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
112 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
142 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
143 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
174 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
175 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
203 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
204 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
234 ; CHECK: or $[[R15:[0-9]+]], $[[R14]], $[[R11]]
235 ; CHECK: sc $[[R15]], 0($[[R2]])
[all …]
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.cpp | 46 : MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST), TII(tii) {} in MBlazeRegisterInfo()
67 case MBlaze::R15 : return 15; in getRegisterNumbering()
132 case 15 : return MBlaze::R15; in getRegisterFromNumbering()
235 Reserved.set(MBlaze::R15); in getReservedRegs()
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| D | MBlazeFrameLowering.cpp | 373 .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset); in emitPrologue()
416 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R15) in emitEpilogue()
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| D | MBlazeISelDAGToDAG.cpp | 235 SDValue GPReg = CurDAG->getRegister(MBlaze::R15, MVT::i32); in Select()
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| D | MBlazeRegisterInfo.td | 57 def R15 : MBlazeGPRReg< 15, "r15">, DwarfRegNum<[15]>;
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 86 case X86::ESI: case X86::R15: return 5; in getCompactUnwindRegNum()
104 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: in getSEHRegNum()
338 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCalleeSavedRegs()
343 X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCalleeSavedRegs()
348 X86::R12, X86::R13, X86::R14, X86::R15, in getCalleeSavedRegs()
410 X86::R12, X86::R13, X86::R14, X86::R15 in getReservedRegs()
688 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
725 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
761 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
797 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
[all …]
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| D | X86RegisterInfo.td | 142 def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
278 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
314 RBX, R14, R15, R12, R13, RBP, RSP, RIP)> {
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 26 R12, R13, R14, R15, R16, R17, R18, R19, R20,
43 R12, R13, R14, R15, R16, R17, R18, R19, R20,
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| D | SPURegisterInfo.cpp | 69 case SPU::R15: return 15; in getRegisterNumbering()
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| /external/kernel-headers/original/asm-x86/ |
| D | ptrace-abi.h | 28 #define R15 0 macro
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.h | 170 {PPC::R15, -68}, in getCalleeSavedSpillSlots()
249 {PPC::R15, -132}, in getCalleeSavedSpillSlots()
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| D | PPCRegisterInfo.cpp | 91 case R15: case X15: case F15: case V15: case CR3UN: return 15; in getRegisterNumbering()
149 PPC::R13, PPC::R14, PPC::R15, in getCalleeSavedRegs()
175 PPC::R14, PPC::R15, in getCalleeSavedRegs()
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| D | PPCRegisterInfo.td | 83 def R15 : GPR<15, "r15">, DwarfRegNum<[-2, 15]>;
117 def X15 : GP8<R15, "r15">, DwarfRegNum<[15, -2]>;
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| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| D | MBlazeMCTargetDesc.cpp | 45 InitMBlazeMCRegisterInfo(X, MBlaze::R15); in createMBlazeMCRegisterInfo()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 19 // i16 are returned in registers R15, R14, R13, R12
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 176 ENTRY(R15)
194 ENTRY(R15)
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| /external/valgrind/main/VEX/auxprogs/ |
| D | genoffsets.c | 114 GENOFFSET(AMD64,amd64,R15); in foo()
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 156 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: in getX86RegNum()
228 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: in InitLLVM2SEHRegisterMapping()
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| /external/llvm/test/CodeGen/X86/ |
| D | ghc-cc64.ll | 14 @splim = external global i64 ; assigned to register: R15
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| /external/llvm/lib/Target/PTX/ |
| D | PTXCallingConv.td | 19 …CCIfType<[i32,f32], CCAssignToReg<[R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24…
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| /external/v8/src/ |
| D | platform-linux.cc | 832 enum ArmRegisters {R15 = 15, R13 = 13, R11 = 11}; enumerator
883 sample->pc = reinterpret_cast<Address>(mcontext.gregs[R15]); in ProfilerSignalHandler()
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| /external/valgrind/main/coregrind/m_sigframe/ |
| D | sigframe-amd64-linux.c | 351 SC2(r15,R15); in synth_ucontext()
|