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Searched refs:R8 (Results 1 – 25 of 59) sorted by relevance

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/external/llvm/test/TableGen/
DTargetInstrInfo.td35 def R8 : RegisterClass;
87 def MOV8rr : Inst<(ops R8:$dst, R8:$src),
89 [(set R8:$dst, R8:$src)]>;
92 def MOV8ri : Inst<(ops R8:$dst, imm8:$src),
94 [(set R8:$dst, imm8:$src)]>;
101 def AND8rr : Inst<(ops R8:$dst, R8:$src1, R8:$src2),
103 [(set R8:$dst, (and R8:$src1, R8:$src2))]>;
/external/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.cpp67 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, in getCalleeSavedRegs()
79 ARM::R11, ARM::R10, ARM::R8, in getCalleeSavedRegs()
409 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, in getRawAllocationOrder()
416 ARM::R8, ARM::R10 in getRawAllocationOrder()
421 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, in getRawAllocationOrder()
428 ARM::R8, ARM::R10 in getRawAllocationOrder()
433 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, in getRawAllocationOrder()
440 ARM::R8 in getRawAllocationOrder()
446 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, in getRawAllocationOrder()
451 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, in getRawAllocationOrder()
[all …]
DARMBaseRegisterInfo.h58 case R8: case R9: case R10: case R11: in isARMArea1Register()
69 case R8: case R9: case R10: case R11: in isARMArea2Register()
DARMBaseInfo.h166 case R8: case S8: case D8: case Q8: return 8; in getARMRegisterNumbering()
/external/llvm/test/CodeGen/Blackfin/
Djumptable.ll43 %R8 = and i32 %A, %B ; <i32> [#uses=1]
44 ret i32 %R8
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td34 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
51 R4, R5, R6, R7, R8, R9, R10)>;
DXCoreRegisterInfo.cpp80 XCore::R8, XCore::R9, XCore::R10, XCore::LR, in getCalleeSavedRegs()
/external/llvm/lib/Target/CellSPU/
DSPUCallingConv.td25 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
42 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
/external/llvm/lib/Target/PowerPC/
DPPCCallingConv.td25 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
42 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
75 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
/external/kernel-headers/original/asm-x86/
Dptrace-abi.h38 #define R8 72 macro
/external/llvm/lib/Target/X86/
DX86RegisterInfo.cpp97 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: in getSEHRegNum()
409 X86::R8, X86::R9, X86::R10, X86::R11, in getReservedRegs()
674 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: in getX86SubSuperRegister()
711 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: in getX86SubSuperRegister()
747 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: in getX86SubSuperRegister()
783 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: in getX86SubSuperRegister()
784 return X86::R8; in getX86SubSuperRegister()
DX86CallingConv.td148 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
206 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
209 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
215 [RCX , RDX , R8 , R9 ]>>,
232 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
DX86RegisterInfo.td135 def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
313 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
357 R8, R9, R11, RIP)> {
364 R8, R9, R11)>;
DX86InstrControl.td215 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
247 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
280 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
/external/llvm/lib/Target/Alpha/
DAlphaRegisterInfo.td46 def R8 : GPR< 8, "$8">, DwarfRegNum<[8]>;
115 R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
/external/llvm/lib/Target/MBlaze/
DMBlazeRegisterInfo.cpp60 case MBlaze::R8 : return 8; in getRegisterNumbering()
125 case 8 : return MBlaze::R8; in getRegisterFromNumbering()
DMBlazeRegisterInfo.td50 def R8 : MBlazeGPRReg< 8, "r8">, DwarfRegNum<[8]>;
/external/valgrind/main/coregrind/m_sigframe/
Dsigframe-arm-linux.c135 SC2(r8,R8); in synth_ucontext()
308 REST(r8,R8); in VG_()
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h169 ENTRY(R8) \
187 ENTRY(R8) \
/external/valgrind/main/VEX/auxprogs/
Dgenoffsets.c107 GENOFFSET(AMD64,amd64,R8); in foo()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp142 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: in getX86RegNum()
221 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: in InitLLVM2SEHRegisterMapping()
/external/llvm/test/CodeGen/X86/
Dghc-cc64.ll12 @r5 = external global i64 ; assigned to register: R8
/external/llvm/test/CodeGen/Mips/
Datomic.ll223 ; CHECK: andi $[[R8:[0-9]+]], $4, 255
224 ; CHECK: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]]
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/en-US/
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/external/llvm/lib/Target/PTX/
DPTXCallingConv.td27 CCIfType<[i32,f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11]>>,

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