| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 100 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
104 ; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
131 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
135 ; CHECK: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
162 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
166 ; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
194 ; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
199 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R9]]
224 ; CHECK: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]]
231 ; CHECK: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]]
|
| /external/llvm/test/CodeGen/Blackfin/ |
| D | jumptable.ll | 46 %R9 = or i32 %A, %B ; <i32> [#uses=1]
47 ret i32 %R9
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 67 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, in getCalleeSavedRegs()
103 Reserved.set(ARM::R9); in getReservedRegs()
131 case ARM::R9: in isReservedReg()
411 ARM::R9, ARM::R11 in getRawAllocationOrder()
414 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, in getRawAllocationOrder()
423 ARM::R9, ARM::R11 in getRawAllocationOrder()
426 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, in getRawAllocationOrder()
435 ARM::R9 in getRawAllocationOrder()
438 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, in getRawAllocationOrder()
685 case ARM::R9: in getRegisterPairEven()
[all …]
|
| D | ARMBaseRegisterInfo.h | 58 case R8: case R9: case R10: case R11: in isARMArea1Register()
69 case R8: case R9: case R10: case R11: in isARMArea2Register()
|
| D | ARMBaseInfo.h | 167 case R9: case S9: case D9: case Q9: return 9; in getARMRegisterNumbering()
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 35 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
51 R4, R5, R6, R7, R8, R9, R10)>;
|
| D | XCoreRegisterInfo.cpp | 80 XCore::R8, XCore::R9, XCore::R10, XCore::LR, in getCalleeSavedRegs()
|
| /external/llvm/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 25 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
42 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 25 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
42 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
75 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
|
| /external/kernel-headers/original/asm-x86/ |
| D | ptrace-abi.h | 37 #define R9 64 macro
|
| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 98 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: in getSEHRegNum()
409 X86::R8, X86::R9, X86::R10, X86::R11, in getReservedRegs()
676 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegister()
713 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegister()
749 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegister()
785 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegister()
786 return X86::R9; in getX86SubSuperRegister()
|
| D | X86CallingConv.td | 148 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
206 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
209 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
215 [RCX , RDX , R8 , R9 ]>>,
232 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
|
| D | X86RegisterInfo.td | 136 def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
313 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
357 R8, R9, R11, RIP)> {
364 R8, R9, R11)>;
|
| D | X86InstrControl.td | 215 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
247 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
280 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
|
| /external/llvm/lib/Target/Alpha/ |
| D | AlphaRegisterInfo.td | 47 def R9 : GPR< 9, "$9">, DwarfRegNum<[9]>;
122 R9, R10, R11, R12, R13, R14,
|
| D | AlphaRegisterInfo.cpp | 60 Alpha::R9, Alpha::R10, in getCalleeSavedRegs()
|
| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.cpp | 61 case MBlaze::R9 : return 9; in getRegisterNumbering()
126 case 9 : return MBlaze::R9; in getRegisterFromNumbering()
|
| D | MBlazeRegisterInfo.td | 51 def R9 : MBlazeGPRReg< 9, "r9">, DwarfRegNum<[9]>;
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| D | sigframe-arm-linux.c | 136 SC2(r9,R9); in synth_ucontext()
309 REST(r9,R9); in VG_()
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 170 ENTRY(R9) \
188 ENTRY(R9) \
|
| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/en-US/ |
| D | en-US_lh0_kdt_mgc2.pkb | 69 �������8���[� �����ͅ���k� �R�x0e_������Xl��@���`YD�R9��
|
| /external/valgrind/main/VEX/auxprogs/ |
| D | genoffsets.c | 108 GENOFFSET(AMD64,amd64,R9); in foo()
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 144 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: in getX86RegNum()
222 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: in InitLLVM2SEHRegisterMapping()
|
| /external/llvm/test/CodeGen/X86/ |
| D | ghc-cc64.ll | 13 @r6 = external global i64 ; assigned to register: R9
|
| /external/llvm/lib/Target/PTX/ |
| D | PTXCallingConv.td | 27 CCIfType<[i32,f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11]>>,
|