Home
last modified time | relevance | path

Searched refs:REG (Results 1 – 25 of 29) sorted by relevance

12

/external/qemu/
Dhostregs_helper.h29 #define DO_REG(REG) \ argument
30 register host_reg_t reg_AREG##REG asm(AREG##REG); \
31 volatile host_reg_t saved_AREG##REG;
35 #define DO_REG(REG) \ argument
36 __asm__ __volatile__ ("" : "=r" (reg_AREG##REG)); \
37 saved_AREG##REG = reg_AREG##REG;
41 #define DO_REG(REG) \ argument
42 reg_AREG##REG = saved_AREG##REG; \
43 __asm__ __volatile__ ("" : : "r" (reg_AREG##REG));
/external/llvm/utils/TableGen/
DEDEmitter.cpp243 #define REG(str) if (name == str) SET("kOperandTypeRegister"); macro
256 REG("GR8"); in X86TypeFromOpName()
257 REG("GR8_NOREX"); in X86TypeFromOpName()
258 REG("GR16"); in X86TypeFromOpName()
259 REG("GR32"); in X86TypeFromOpName()
260 REG("GR32_NOREX"); in X86TypeFromOpName()
261 REG("GR32_TC"); in X86TypeFromOpName()
262 REG("FR32"); in X86TypeFromOpName()
263 REG("RFP32"); in X86TypeFromOpName()
264 REG("GR64"); in X86TypeFromOpName()
[all …]
/external/llvm/test/CodeGen/X86/
Dxor.ll61 ; X64: notl [[REG:%[a-z]+]]
62 ; X64: andl {{.*}}[[REG]]
64 ; X32: notl [[REG:%[a-z]+]]
65 ; X32: andl {{.*}}[[REG]]
83 ; X64: notl [[REG:%[a-z]+]]
84 ; X64: andl {{.*}}[[REG]]
86 ; X32: notl [[REG:%[a-z]+]]
87 ; X32: andl {{.*}}[[REG]]
105 ; X64: notb [[REG:%[a-z]+]]
106 ; X64: andb {{.*}}[[REG]]
[all …]
Dzext-extract_subreg.ll14 ; CHECK: movl (%{{.*}}), [[REG:%[a-z]+]]
15 ; CHECK-NOT: movl [[REG]], [[REG]]
16 ; CHECK-NEXT: testl [[REG]], [[REG]]
Dloop-strength-reduce-2.ll9 ; PIC: movl $4, -4([[REG:%e[a-z]+]])
10 ; PIC: movl $5, ([[REG]])
11 ; PIC: addl $4, [[REG]]
D2010-05-05-LocalAllocEarlyClobber.ll16 ; CHECK: deafbeef, [[REG:%e.x]]
17 ; CHECK-NOT: [[REG]]
D2009-11-16-MachineLICM.ll13 ; CHECK: movq _g@GOTPCREL(%rip), [[REG:%[a-z]+]]
/external/llvm/test/CodeGen/ARM/
Dva_arg.ll6 ; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
7 ; CHECK: bfc [[REG]], #0, #3
22 ; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
23 ; CHECK: bfc [[REG]], #0, #3
D2011-03-23-PeepholeBug.ll27 ; CHECK: subs [[REG:r[0-9]+]], #1
28 ; CHECK: cmp [[REG]], #0
/external/llvm/test/CodeGen/XCore/
Dmul64.ll11 ; CHECK: ldc [[REG:r[0-9]+]], 0
12 ; CHECK-NEXT: lmul {{.*}}, [[REG]], [[REG]]
/external/clang/lib/StaticAnalyzer/Core/
DMemRegion.cpp483 template <typename REG>
484 const REG *MemRegionManager::LazyAllocate(REG*& region) { in LazyAllocate()
486 region = (REG*) A.Allocate<REG>(); in LazyAllocate()
487 new (region) REG(this); in LazyAllocate()
493 template <typename REG, typename ARG>
494 const REG *MemRegionManager::LazyAllocate(REG*& region, ARG a) { in LazyAllocate()
496 region = (REG*) A.Allocate<REG>(); in LazyAllocate()
497 new (region) REG(this, a); in LazyAllocate()
/external/llvm/test/CodeGen/PowerPC/
D2007-04-30-InlineAsmEarlyClobber.ll5 ; CHECK: subfc [[REG:r.]],
6 ; CHECK-NOT: [[REG]]
/external/llvm/test/CodeGen/MBlaze/
Dloop.ll34 ; CHECK: cmp [[REG:r[0-9]*]]
37 ; CHECK: {{beqid|bneid}} [[REG]]
Djumptable.ll21 ; CHECK: lw [[REG:r[0-9]*]]
22 ; CHECK: brad [[REG]]
/external/valgrind/main/coregrind/m_sigframe/
Dsigframe-arm-linux.c126 # define SC2(reg,REG) sc->arm_##reg = tst->arch.vex.guest_##REG in synth_ucontext() argument
299 # define REST(reg,REG) tst->arch.vex.guest_##REG = mc->arm_##reg; in VG_() argument
Dsigframe-amd64-linux.c343 # define SC2(reg,REG) sc->reg = tst->arch.vex.guest_##REG in synth_ucontext() argument
Dsigframe-x86-linux.c367 # define SC2(reg,REG) sc->reg = tst->arch.vex.guest_##REG in synth_ucontext() argument
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
DMemRegion.h1061 template <typename REG>
1062 const REG* LazyAllocate(REG*& region);
1064 template <typename REG, typename ARG>
1065 const REG* LazyAllocate(REG*& region, ARG a);
/external/libpng/scripts/
Dmakefile.amiga18 CFLAGS= NOSTKCHK PARMS=REG OPTIMIZE OPTGO OPTPEEP OPTINLOCAL OPTINL\
/external/llvm/lib/Target/X86/
DX86InstrCompiler.td1063 "", // orw/addw REG, REG
1066 "", // orl/addl REG, REG
1069 "", // orq/addq REG, REG
1078 "", // orw/addw REG, imm8
1081 "", // orw/addw REG, imm
1086 "", // orl/addl REG, imm8
1089 "", // orl/addl REG, imm
1095 "", // orq/addq REG, imm8
1100 "", // orq/addq REG, imm
/external/wpa_supplicant_8/hostapd/
DREADME-WPS276 WPS-REG-SUCCESS <Enrollee MAC address <UUID-E>
278 <2>WPS-REG-SUCCESS 02:66:a0:ee:17:27 2b7093f1-d6fb-5108-adbb-bea66bb87333
/external/webkit/Source/WebCore/html/parser/
DHTMLEntityNames.in422 "REG;","U+000AE"
423 "REG","U+000AE"
/external/oprofile/events/ia64/itanium2/
Devents11 …unters:0,1,2,3 um:zero minimum:5000 name:INST_DISPERSED : Syllables Dispersed from REN to REG stage
/external/valgrind/tsan/
Dts_pin.cc187 REG tls_reg;
/external/harfbuzz/contrib/tables/
DGraphemeBreakProperty.txt874 B809..B823 ; LVT # Lo [27] HANGUL SYLLABLE REG..HANGUL SYLLABLE REH

12