| /external/qemu/tcg/ppc/ |
| D | tcg-target.c | 332 #define RLWINM OPCD(21) macro
556 tcg_out32 (s, (RLWINM in tcg_out_qemu_ld()
571 tcg_out32 (s, (RLWINM in tcg_out_qemu_ld()
752 tcg_out32 (s, (RLWINM in tcg_out_qemu_st()
767 tcg_out32 (s, (RLWINM in tcg_out_qemu_st()
804 tcg_out32 (s, (RLWINM in tcg_out_qemu_st()
812 tcg_out32 (s, (RLWINM in tcg_out_qemu_st()
1149 tcg_out32 (s, (RLWINM in tcg_out_setcond()
1216 tcg_out32 (s, (RLWINM in tcg_out_setcond()
1236 tcg_out32 (s, (RLWINM in tcg_out_setcond2()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 627 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); in SelectSETCC()
639 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); in SelectSETCC()
646 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); in SelectSETCC()
676 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); in SelectSETCC()
680 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), in SelectSETCC()
712 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); in SelectSETCC()
716 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); in SelectSETCC()
728 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); in SelectSETCC()
938 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); in Select()
947 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); in Select()
[all …]
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| D | PPCInstrInfo.cpp | 407 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) in StoreRegToStackSlot()
542 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg) in LoadRegFromStackSlot()
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| D | PPCInstrInfo.td | 1329 def RLWINM : MForm_2<21,
1371 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1373 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1379 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
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| D | PPCRegisterInfo.cpp | 522 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) in lowerCRSpilling()
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| D | PPCFrameLowering.cpp | 359 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) in emitPrologue()
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| D | PPCISelLowering.cpp | 4770 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) in EmitPartwordAtomicBinary()
4778 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitPartwordAtomicBinary()
5102 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) in EmitInstrWithCustomInserter()
5110 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitInstrWithCustomInserter()
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| /external/qemu/tcg/ppc64/ |
| D | tcg-target.c | 318 #define RLWINM OPCD( 21) macro
575 tcg_out32 (s, (RLWINM in tcg_out_tlb_read()
585 tcg_out32 (s, (RLWINM in tcg_out_tlb_read()
1083 tcg_out32 (s, (RLWINM in tcg_out_setcond()
1151 tcg_out32 (s, (RLWINM in tcg_out_setcond()
1406 tcg_out32 (s, (RLWINM in tcg_out_op()
1420 tcg_out32 (s, (RLWINM in tcg_out_op()
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| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| D | PPCInstPrinter.cpp | 35 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
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