| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ThumbDisassemblerCore.h | 105 static inline bool IsGPR(unsigned RegClass) { in IsGPR() argument
106 return RegClass == ARM::GPRRegClassID || RegClass == ARM::rGPRRegClassID; in IsGPR()
358 assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID in DisassembleThumb1General()
374 if (OpInfo[OpIdx].RegClass == ARM::CCRRegClassID) { in DisassembleThumb1General()
382 if (OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID) { in DisassembleThumb1General()
395 if (OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID) { in DisassembleThumb1General()
400 assert(OpInfo[OpIdx].RegClass < 0 && in DisassembleThumb1General()
434 assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID && in DisassembleThumb1DP()
435 (OpInfo[1].RegClass == ARM::CCRRegClassID in DisassembleThumb1DP()
436 || OpInfo[1].RegClass == ARM::tGPRRegClassID) in DisassembleThumb1DP()
[all …]
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| D | ARMDisassemblerCore.cpp | 602 && OpInfo[0].RegClass == ARM::GPRRegClassID in DisassembleMulFrm()
603 && OpInfo[1].RegClass == ARM::GPRRegClassID in DisassembleMulFrm()
604 && OpInfo[2].RegClass == ARM::GPRRegClassID in DisassembleMulFrm()
613 assert(NumOps >= 4 && OpInfo[3].RegClass == ARM::GPRRegClassID && in DisassembleMulFrm()
633 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) { in DisassembleMulFrm()
812 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID && in DisassembleBrFrm()
821 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID && in DisassembleBrFrm()
831 assert(NumOps >= 1 && OpInfo[1].RegClass == ARM::GPRRegClassID && in DisassembleBrFrm()
877 assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Imm operand expected"); in DisassembleBrFrm()
920 assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID && in DisassembleBrMiscFrm()
[all …]
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| /external/llvm/lib/Target/ |
| D | TargetInstrInfo.cpp | 36 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
38 return TRI->getPointerRegClass(RegClass); in getRegClass()
41 if (RegClass < 0) in getRegClass()
45 return TRI->getRegClass(RegClass); in getRegClass()
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterScavenging.h | 107 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
118 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
120 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister() argument
121 return scavengeRegister(RegClass, MBBI, SPAdj); in scavengeRegister()
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| D | MachineRegisterInfo.h | 208 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrArithmetic.td | 515 /// RegClass - This is the register class associated with this type. For
517 RegisterClass RegClass = regclass;
606 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
613 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
614 [(set typeinfo.RegClass:$dst,
615 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
623 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
630 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
631 [(set typeinfo.RegClass:$dst, EFLAGS,
632 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 67 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister() argument
68 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
69 assert(RegClass->isAllocatable() && in createVirtualRegister()
79 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
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| D | RegisterClassInfo.h | 40 OwningArrayPtr<RCInfo> RegClass; variable
64 const RCInfo &RCI = RegClass[RC->getID()]; in get()
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| D | RegisterClassInfo.cpp | 37 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
71 RCInfo &RCI = RegClass[RC->getID()]; in compute()
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 61 short RegClass;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1357 SDValue RegClass = in PairSRegs() local
1361 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairSRegs()
1369 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32); in PairDRegs() local
1372 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairDRegs()
1380 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); in PairQRegs() local
1383 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in PairQRegs()
1392 SDValue RegClass = in QuadSRegs() local
1398 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in QuadSRegs()
1408 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); in QuadDRegs() local
1413 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in QuadDRegs()
[all …]
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| /external/llvm/utils/TableGen/ |
| D | CodeGenDAGPatterns.cpp | 1250 Record *RegClass = R->getValueAsDef("RegClass"); in getImplicitType() local
1252 return EEVT::TypeSet(T.getRegisterClass(RegClass).getValueTypes()); in getImplicitType()
1538 Record *RegClass = ResultNode->getValueAsDef("RegClass"); in ApplyTypeConstraints() local
1540 CDP.getTargetInfo().getRegisterClass(RegClass); in ApplyTypeConstraints()
1601 Record *RegClass = OperandNode->getValueAsDef("RegClass"); in ApplyTypeConstraints() local
1603 CDP.getTargetInfo().getRegisterClass(RegClass); in ApplyTypeConstraints()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 287 unsigned &RegClass, unsigned &Cost) { in GetCostForDef() argument
299 RegClass = RC->getID(); in GetCostForDef()
307 RegClass = RC->getID(); in GetCostForDef()
312 RegClass = TLI->getRepRegClassFor(VT)->getID(); in GetCostForDef()
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| /external/llvm/include/llvm/Target/ |
| D | Target.td | 145 // dags: (RegClass SubRegIndex, SubRegindex, ...)
522 // RegClass - The register class of the operand.
523 RegisterClass RegClass = regclass;
|