| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 96 const std::vector<CodeGenRegister*> &Regs, in EmitRegMapping() argument
105 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in EmitRegMapping()
106 Record *Reg = Regs[i]->TheDef; in EmitRegMapping()
159 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in EmitRegMapping()
160 Record *Reg = Regs[i]->TheDef; in EmitRegMapping()
229 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); in runMCDesc() local
232 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in runMCDesc()
233 const CodeGenRegister *Reg = Regs[i]; in runMCDesc()
249 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in runMCDesc()
250 const CodeGenRegister &Reg = *Regs[i]; in runMCDesc()
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| D | CodeGenRegisters.cpp | 372 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
373 std::sort(Regs.begin(), Regs.end(), LessRecord()); in CodeGenRegBank()
374 Registers.reserve(Regs.size()); in CodeGenRegBank()
376 for (unsigned i = 0, e = Regs.size(); i != e; ++i) in CodeGenRegBank()
377 getReg(Regs[i]); in CodeGenRegBank()
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| D | RegisterInfoEmitter.h | 52 const std::vector<CodeGenRegister*> &Regs, bool isCtor);
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| D | CodeGenTarget.cpp | 175 const std::vector<CodeGenRegister*> &Regs = getRegBank().getRegisters(); in getRegisterByName() local
176 for (unsigned i = 0, e = Regs.size(); i != e; ++i) in getRegisterByName()
177 if (Regs[i]->TheDef->getValueAsString("AsmName") == Name) in getRegisterByName()
178 return Regs[i]; in getRegisterByName()
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| D | AsmMatcherEmitter.cpp | 1779 const std::vector<CodeGenRegister*> &Regs = in EmitMatchRegisterName() local
1781 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in EmitMatchRegisterName()
1782 const CodeGenRegister *Reg = Regs[i]; in EmitMatchRegisterName()
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 232 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { in getFirstUnallocated() argument
234 if (!isAllocated(Regs[i])) in getFirstUnallocated()
259 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { in AllocateReg() argument
260 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
265 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg()
271 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, in AllocateReg() argument
273 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
278 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; in AllocateReg()
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| D | RegisterScavenging.h | 141 void setUsed(BitVector &Regs) { in setUsed() argument
142 RegsAvailable &= ~Regs; in setUsed()
144 void setUnused(BitVector &Regs) { in setUnused() argument
145 RegsAvailable |= Regs; in setUnused()
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| D | MachineRegisterInfo.h | 250 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } in addPhysRegsUsed() argument
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 547 SmallVector<std::pair<unsigned,bool>, 4> Regs; in emitPushInst() local
575 Regs.push_back(std::make_pair(Reg, isKill)); in emitPushInst()
578 if (Regs.empty()) in emitPushInst()
580 if (Regs.size() > 1 || StrOpc== 0) { in emitPushInst()
584 for (unsigned i = 0, e = Regs.size(); i < e; ++i) in emitPushInst()
585 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); in emitPushInst()
586 } else if (Regs.size() == 1) { in emitPushInst()
589 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) in emitPushInst()
600 Regs.clear(); in emitPushInst()
620 SmallVector<unsigned, 4> Regs; in emitPopInst() local
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| D | ARMLoadStoreOptimizer.cpp | 92 DebugLoc dl, SmallVector<std::pair<unsigned, bool>, 8> &Regs);
293 SmallVector<std::pair<unsigned, bool>, 8> &Regs) { in MergeOps() argument
295 unsigned NumRegs = Regs.size(); in MergeOps()
325 NewBase = Regs[NumRegs-1].first; in MergeOps()
358 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) in MergeOps()
359 | getKillRegState(Regs[i].second)); in MergeOps()
394 SmallVector<std::pair<unsigned, bool>, 8> Regs; in MergeOpsUpdate() local
400 Regs.push_back(std::make_pair(Reg, isKill)); in MergeOpsUpdate()
407 Pred, PredReg, Scratch, dl, Regs)) in MergeOpsUpdate()
414 if (Regs[i-memOpsBegin].second) { in MergeOpsUpdate()
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| D | Thumb2SizeReduction.cpp | 189 for (const unsigned *Regs = MCID.ImplicitDefs; *Regs; ++Regs) in HasImplicitCPSRDef() local
190 if (*Regs == ARM::CPSR) in HasImplicitCPSRDef()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 71 std::vector<unsigned> &Regs, in GetGroupRegs() argument
76 Regs.push_back(Reg); in GetGroupRegs()
558 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
559 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); in FindSuitableFreeRegisters()
560 assert(Regs.size() > 0 && "Empty register group!"); in FindSuitableFreeRegisters()
561 if (Regs.size() == 0) in FindSuitableFreeRegisters()
571 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
572 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
591 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
592 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
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| D | LocalStackSlotAllocation.cpp | 201 lookupCandidateBaseReg(const SmallVector<std::pair<unsigned, int64_t>, 8> &Regs, in lookupCandidateBaseReg() argument
207 unsigned e = Regs.size(); in lookupCandidateBaseReg()
209 RegOffset = Regs[i]; in lookupCandidateBaseReg()
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| D | AggressiveAntiDepBreaker.h | 97 std::vector<unsigned> &Regs,
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 674 SmallPtrSet<const SCEV *, 16> &Regs,
685 SmallPtrSet<const SCEV *, 16> &Regs,
689 SmallPtrSet<const SCEV *, 16> &Regs,
698 SmallPtrSet<const SCEV *, 16> &Regs, in RateRegister() argument
724 if (!Regs.count(AR->getStart())) in RateRegister()
725 RateRegister(AR->getStart(), Regs, L, SE, DT); in RateRegister()
731 if (!Regs.count(AR->getStart())) in RateRegister()
732 RateRegister(AR->getOperand(1), Regs, L, SE, DT); in RateRegister()
752 SmallPtrSet<const SCEV *, 16> &Regs, in RatePrimaryRegister() argument
755 if (Regs.insert(Reg)) in RatePrimaryRegister()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 572 SmallVector<unsigned, 4> Regs; member
578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} in RegsForValue()
589 Regs.push_back(Reg + i); in RegsForValue()
609 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); in append()
664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); in getCopyFromRegs()
666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); in getCopyFromRegs()
675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || in getCopyFromRegs()
680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); in getCopyFromRegs()
737 unsigned NumRegs = Regs.size(); in getCopyToRegs()
754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); in getCopyToRegs()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 860 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, in CreateRegList() argument
864 if (ARM::DPRRegClass.contains(Regs.front().first)) in CreateRegList()
866 else if (ARM::SPRRegClass.contains(Regs.front().first)) in CreateRegList()
871 I = Regs.begin(), E = Regs.end(); I != E; ++I) in CreateRegList()
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassemblerCore.cpp | 2118 unsigned Regs = isSPVFP ? Imm8 : Imm8/2; in DisassembleVFPLdStMulFrm() local
2121 if (Regs == 0 || (RegD + Regs) > 32 || (!isSPVFP && Regs > 16)) in DisassembleVFPLdStMulFrm()
2124 for (unsigned i = 0; i < Regs; ++i) { in DisassembleVFPLdStMulFrm()
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| /external/llvm/include/llvm/Target/ |
| D | Target.td | 226 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
230 list<dag> SubRegs = Regs;
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| /external/webkit/PerformanceTests/Parser/resources/ |
| D | final-url-en | 55170 http://www.marcorsyscom.usmc.mil/sites/mcub/PAGES/Uniform%20Regs%20Chapters/Chapter%2010%5CChapter%…
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