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Searched refs:ShiftAmt (Results 1 – 14 of 14) sorted by relevance

/external/llvm/lib/Transforms/InstCombine/
DInstCombineSimplifyDemanded.cpp579 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in SimplifyDemandedUseBits() local
580 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt)); in SimplifyDemandedUseBits()
585 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1); in SimplifyDemandedUseBits()
587 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt); in SimplifyDemandedUseBits()
593 KnownZero <<= ShiftAmt; in SimplifyDemandedUseBits()
594 KnownOne <<= ShiftAmt; in SimplifyDemandedUseBits()
596 if (ShiftAmt) in SimplifyDemandedUseBits()
597 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt); in SimplifyDemandedUseBits()
603 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in SimplifyDemandedUseBits() local
606 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt)); in SimplifyDemandedUseBits()
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DInstCombineCasts.cpp564 uint32_t ShiftAmt = KnownZeroMask.logBase2(); in transformZExtICmp() local
566 if (ShiftAmt) { in transformZExtICmp()
569 In = Builder->CreateLShr(In, ConstantInt::get(In->getType(),ShiftAmt), in transformZExtICmp()
935 unsigned ShiftAmt = KnownZeroMask.countTrailingZeros(); in transformSExtICmp() local
937 if (ShiftAmt) in transformSExtICmp()
939 ConstantInt::get(In->getType(), ShiftAmt)); in transformSExtICmp()
949 unsigned ShiftAmt = KnownZeroMask.countLeadingZeros(); in transformSExtICmp() local
951 if (ShiftAmt) in transformSExtICmp()
953 ConstantInt::get(In->getType(), ShiftAmt)); in transformSExtICmp()
/external/llvm/lib/Target/CellSPU/
DSPUISelDAGToDAG.cpp917 SDValue ShiftAmt = N->getOperand(1); in SelectSHLi64() local
918 EVT ShiftAmtVT = ShiftAmt.getValueType(); in SelectSHLi64()
934 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) { in SelectSHLi64()
954 ShiftAmt, in SelectSHLi64()
958 ShiftAmt, in SelectSHLi64()
985 SDValue ShiftAmt = N->getOperand(1); in SelectSRLi64() local
986 EVT ShiftAmtVT = ShiftAmt.getValueType(); in SelectSRLi64()
993 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) { in SelectSRLi64()
1013 ShiftAmt, in SelectSRLi64()
1017 ShiftAmt, in SelectSRLi64()
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/external/llvm/lib/Analysis/
DValueTracking.cpp329 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); in ComputeMaskedBits() local
330 APInt Mask2(Mask.lshr(ShiftAmt)); in ComputeMaskedBits()
334 KnownZero <<= ShiftAmt; in ComputeMaskedBits()
335 KnownOne <<= ShiftAmt; in ComputeMaskedBits()
336 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt); // low bits known 0 in ComputeMaskedBits()
344 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); in ComputeMaskedBits() local
347 APInt Mask2(Mask.shl(ShiftAmt)); in ComputeMaskedBits()
351 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt); in ComputeMaskedBits()
352 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt); in ComputeMaskedBits()
354 KnownZero |= APInt::getHighBitsSet(BitWidth, ShiftAmt); in ComputeMaskedBits()
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DConstantFolding.cpp127 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1); in FoldBitCast() local
138 ConstantInt::get(Src->getType(), ShiftAmt)); in FoldBitCast()
139 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize; in FoldBitCast()
157 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1); in FoldBitCast() local
162 ConstantInt::get(Src->getType(), ShiftAmt)); in FoldBitCast()
163 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize; in FoldBitCast()
/external/llvm/lib/Target/ARM/
DARMCodeEmitter.cpp1511 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); in emitMiscArithInstruction() local
1513 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); in emitMiscArithInstruction()
1514 if (ShiftAmt == 32) in emitMiscArithInstruction()
1515 ShiftAmt = 0; in emitMiscArithInstruction()
1517 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); in emitMiscArithInstruction()
1518 Binary |= ShiftAmt << ARMII::ShiftShift; in emitMiscArithInstruction()
1554 unsigned ShiftAmt = MI.getOperand(3).getImm(); in emitSaturateInstruction() local
1555 if (ShiftAmt == 32 && Opc == ARM_AM::asr) in emitSaturateInstruction()
1556 ShiftAmt = 0; in emitSaturateInstruction()
1557 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); in emitSaturateInstruction()
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DARMISelLowering.cpp5738 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt); in PerformMULCombine() local
5739 ShiftAmt = ShiftAmt & (32 - 1); in PerformMULCombine()
5744 MulAmt >>= ShiftAmt; in PerformMULCombine()
5761 if (ShiftAmt != 0) in PerformMULCombine()
5763 DAG.getConstant(ShiftAmt, MVT::i32)); in PerformMULCombine()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp816 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); in EmitAtomicBinaryPartword() local
872 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); in EmitAtomicBinaryPartword()
876 .addReg(ShiftAmt).addReg(MaskUpper); in EmitAtomicBinaryPartword()
878 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); in EmitAtomicBinaryPartword()
940 .addReg(ShiftAmt).addReg(MaskedOldVal1); in EmitAtomicBinaryPartword()
1037 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); in EmitAtomicCmpSwapPartword() local
1100 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); in EmitAtomicCmpSwapPartword()
1104 .addReg(ShiftAmt).addReg(MaskUpper); in EmitAtomicCmpSwapPartword()
1109 .addReg(ShiftAmt).addReg(MaskedCmpVal); in EmitAtomicCmpSwapPartword()
1113 .addReg(ShiftAmt).addReg(MaskedNewVal); in EmitAtomicCmpSwapPartword()
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/external/llvm/lib/Transforms/Scalar/
DGVN.cpp955 unsigned ShiftAmt; in GetStoreValueForLoad() local
957 ShiftAmt = Offset*8; in GetStoreValueForLoad()
959 ShiftAmt = (StoreSize-LoadSize-Offset)*8; in GetStoreValueForLoad()
961 if (ShiftAmt) in GetStoreValueForLoad()
962 SrcVal = Builder.CreateLShr(SrcVal, ShiftAmt, "tmp"); in GetStoreValueForLoad()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassemblerCore.cpp1634 unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F; in DisassembleArithMiscFrm() local
1640 getImmShiftSE(Opc, ShiftAmt); in DisassembleArithMiscFrm()
1641 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt))); in DisassembleArithMiscFrm()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp584 unsigned ShiftAmt = SVOp->getMaskElt(i); in isVSLDOIShuffleMask() local
585 if (ShiftAmt < i) return -1; in isVSLDOIShuffleMask()
586 ShiftAmt -= i; in isVSLDOIShuffleMask()
591 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) in isVSLDOIShuffleMask()
596 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) in isVSLDOIShuffleMask()
599 return ShiftAmt; in isVSLDOIShuffleMask()
/external/llvm/lib/Support/
DAPInt.cpp2262 unsigned ShiftAmt = (Radix == 16 ? 4 : (Radix == 8 ? 3 : 1)); in toString() local
2268 Tmp = Tmp.lshr(ShiftAmt); in toString()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp8885 uint64_t ShiftAmt = C->getZExtValue(); in LowerShift() local
8890 R, DAG.getConstant(ShiftAmt, MVT::i32)); in LowerShift()
8895 R, DAG.getConstant(ShiftAmt, MVT::i32)); in LowerShift()
8900 R, DAG.getConstant(ShiftAmt, MVT::i32)); in LowerShift()
8905 R, DAG.getConstant(ShiftAmt, MVT::i32)); in LowerShift()
8910 R, DAG.getConstant(ShiftAmt, MVT::i32)); in LowerShift()
8915 R, DAG.getConstant(ShiftAmt, MVT::i32)); in LowerShift()
8920 R, DAG.getConstant(ShiftAmt, MVT::i32)); in LowerShift()
8925 R, DAG.getConstant(ShiftAmt, MVT::i32)); in LowerShift()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp3432 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); in visitSRA() local
3438 if ((ShiftAmt > 0) && in visitSRA()
3443 SDValue Amt = DAG.getConstant(ShiftAmt, in visitSRA()
3590 uint64_t ShiftAmt = N1C->getZExtValue(); in visitSRL() local
3593 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); in visitSRL()