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Searched refs:SimpleTy (Results 1 – 25 of 31) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DValueTypes.h132 SimpleValueType SimpleTy; variable
134 MVT() : SimpleTy((SimpleValueType)(INVALID_SIMPLE_VALUE_TYPE)) {} in MVT()
135 MVT(SimpleValueType SVT) : SimpleTy(SVT) { } in MVT()
137 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
138 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
139 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
140 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
141 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
142 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
146 return ((SimpleTy >= MVT::f32 && SimpleTy <= MVT::ppcf128) || in isFloatingPoint()
[all …]
/external/llvm/include/llvm/Target/
DTargetLowering.h183 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; in getRegClassFor()
195 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy]; in getRepRegClassFor()
203 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy]; in getRepRegClassCostFor()
211 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); in isTypeLegal()
212 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; in isTypeLegal()
226 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy]; in getTypeAction()
230 unsigned I = VT.getSimpleVT().SimpleTy; in setTypeAction()
352 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; in getOperationAction()
380 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; in getLoadExtAction()
397 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy] in getTruncStoreAction()
[all …]
/external/llvm/lib/VMCore/
DValueTypes.cpp90 switch (V.SimpleTy) { in getEVTString()
144 switch (V.SimpleTy) { in getTypeForEVT()
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp1382 switch (NVT.getSimpleVT().SimpleTy) { in SelectAtomicLoadAdd()
1594 switch (NVT.getSimpleVT().SimpleTy) { in SelectAtomicLoadArith()
1798 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1834 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1862 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1870 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1880 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1962 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1970 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1981 switch (NVT.getSimpleVT().SimpleTy) { in Select()
[all …]
DX86FastISel.cpp180 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitLoad()
237 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
275 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
800 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode()
815 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode()
1057 switch (SourceVT.SimpleTy) { in X86SelectBranch()
1948 switch (VT.SimpleTy) { in TargetMaterializeConstant()
2070 switch (VT.SimpleTy) { in TargetMaterializeFloatZero()
DX86RegisterInfo.cpp640 switch (VT.getSimpleVT().SimpleTy) { in getX86SubSuperRegister()
DX86ISelLowering.cpp876 VT.getSimpleVT().SimpleTy, Custom); in X86TargetLowering()
878 VT.getSimpleVT().SimpleTy, Custom); in X86TargetLowering()
880 VT.getSimpleVT().SimpleTy, Custom); in X86TargetLowering()
1280 switch (VT.getSimpleVT().SimpleTy) { in findRepresentativeClass()
5212 switch (VT.getSimpleVT().SimpleTy) { in RewriteAsNarrowerShuffle()
5633 switch(VT.getSimpleVT().SimpleTy) { in getUNPCKLOpcode()
5651 switch(VT.getSimpleVT().SimpleTy) { in getUNPCKHOpcode()
7079 switch (DstTy.getSimpleVT().SimpleTy) { in FP_TO_INTHelper()
7633 switch (VT.getSimpleVT().SimpleTy) { in LowerVSETCC()
9091 switch (VT.getSimpleVT().SimpleTy) { in LowerSIGN_EXTEND_INREG()
[all …]
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp827 switch (VT.getSimpleVT().SimpleTy) { in ARMSimplifyAddress()
874 if (VT.getSimpleVT().SimpleTy == MVT::f32 || in AddLoadStoreOperands()
875 VT.getSimpleVT().SimpleTy == MVT::f64) in AddLoadStoreOperands()
892 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0); in AddLoadStoreOperands()
901 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0); in AddLoadStoreOperands()
913 switch (VT.getSimpleVT().SimpleTy) { in ARMEmitLoad()
966 switch (VT.getSimpleVT().SimpleTy) { in ARMEmitStore()
1096 switch (SourceVT.SimpleTy) { in SelectBranch()
1214 switch (VT.SimpleTy) { in SelectCmp()
2002 switch (SrcVT.getSimpleVT().SimpleTy) { in SelectIntCast()
DARMISelDAGToDAG.cpp1318 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectT2IndexedLoad()
1472 switch (VT.getSimpleVT().SimpleTy) { in SelectVLD()
1600 switch (VT.getSimpleVT().SimpleTy) { in SelectVST()
1754 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDSTLane()
1867 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDDup()
2183 switch (VT.getSimpleVT().SimpleTy) { in SelectCMOVOp()
2464 switch (VT.getSimpleVT().SimpleTy) { in Select()
2483 switch (VT.getSimpleVT().SimpleTy) { in Select()
2502 switch (VT.getSimpleVT().SimpleTy) { in Select()
DARMISelLowering.cpp774 switch (VT.getSimpleVT().SimpleTy) { in findRepresentativeClass()
5613 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { in AddCombineToVPADDL()
7094 switch (VT.getSimpleVT().SimpleTy) { in allowsUnalignedMemoryAccesses()
7110 switch (VT.getSimpleVT().SimpleTy) { in isLegalT1AddressImmediate()
7140 switch (VT.getSimpleVT().SimpleTy) { in isLegalT2AddressImmediate()
7181 switch (VT.getSimpleVT().SimpleTy) { in isLegalAddressImmediate()
7208 switch (VT.getSimpleVT().SimpleTy) { in isLegalT2ScaledAddressingMode()
7266 switch (VT.getSimpleVT().SimpleTy) { in isLegalAddressingMode()
/external/llvm/lib/Target/MSP430/
DMSP430ISelDAGToDAG.cpp309 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
337 switch (VT.SimpleTy) { in SelectIndexedLoad()
DMSP430ISelLowering.cpp326 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
331 << RegVT.getSimpleVT().SimpleTy << "\n"; in LowerCCCArguments()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp362 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP()
2271 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in ExpandFPLibCall()
2288 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in ExpandIntLibCall()
2303 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in isDivRemLibcallAvailable()
2348 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in ExpandDivRemLibCall()
2571 switch (Op0.getValueType().getSimpleVT().SimpleTy) { in ExpandLegalINT_TO_FP()
2618 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); in PromoteLegalINT_TO_FP()
2660 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); in PromoteLegalFP_TO_INT()
2691 switch (VT.getSimpleVT().SimpleTy) { in ExpandBSWAP()
2844 switch (VT.SimpleTy) { in ExpandAtomic()
[all …]
DLegalizeIntegerTypes.cpp1117 switch (VT.SimpleTy) { in ExpandAtomic()
1126 switch (VT.SimpleTy) { in ExpandAtomic()
1135 switch (VT.SimpleTy) { in ExpandAtomic()
1144 switch (VT.SimpleTy) { in ExpandAtomic()
1153 switch (VT.SimpleTy) { in ExpandAtomic()
1162 switch (VT.SimpleTy) { in ExpandAtomic()
1171 switch (VT.SimpleTy) { in ExpandAtomic()
1180 switch (VT.SimpleTy) { in ExpandAtomic()
2661 switch (VT.getSimpleVT().SimpleTy) { in EVTToAPFloatSemantics()
DSelectionDAG.cpp64 switch (VT.getSimpleVT().SimpleTy) { in EVTToAPFloatSemantics()
635 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0; in RemoveNodeFromCSEMaps()
636 ValueTypeNodes[VT.getSimpleVT().SimpleTy] = 0; in RemoveNodeFromCSEMaps()
1162 if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >= in getValueType()
1164 ValueTypeNodes.resize(VT.getSimpleVT().SimpleTy+1); in getValueType()
1167 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT().SimpleTy]; in getValueType()
3355 LVT = (MVT::SimpleValueType)(LVT.SimpleTy - 1); in FindOptimalMemOpLowering()
3370 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1); in FindOptimalMemOpLowering()
3375 VT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy - 1); in FindOptimalMemOpLowering()
5606 return &SimpleVTArray->VTs[VT.getSimpleVT().SimpleTy]; in getValueTypeList()
/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp610 switch (NVT.getSimpleVT().SimpleTy) { in Select()
690 switch (NVT.getSimpleVT().SimpleTy) { in Select()
DSystemZISelLowering.cpp310 switch (LocVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
314 << LocVT.getSimpleVT().SimpleTy in LowerCCCArguments()
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp504 switch(VT.getSimpleVT().SimpleTy){ in getSetCCResultType()
1137 switch (ObjectVT.getSimpleVT().SimpleTy) { in LowerFormalArguments()
1304 switch (Arg.getValueType().getSimpleVT().SimpleTy) { in LowerCall()
1660 switch (VT.getSimpleVT().SimpleTy) { in LowerBUILD_VECTOR()
1953 switch (Op.getValueType().getSimpleVT().SimpleTy) { in LowerSCALAR_TO_VECTOR()
1972 switch (Op0.getValueType().getSimpleVT().SimpleTy) { in LowerSCALAR_TO_VECTOR()
2017 switch (VT.getSimpleVT().SimpleTy) { in LowerEXTRACT_VECTOR_ELT()
2109 switch (VT.getSimpleVT().SimpleTy) { in LowerEXTRACT_VECTOR_ELT()
2351 switch (VT.getSimpleVT().SimpleTy) { in LowerCTPOP()
DSPUISelDAGToDAG.cpp579 switch( VT.SimpleTy ) { in getRC()
660 switch (Op0VT.getSimpleVT().SimpleTy) { in Select()
/external/llvm/lib/Target/Mips/
DMipsISelDAGToDAG.cpp189 N->getValueType(0).getSimpleVT().SimpleTy; in SelectLoadFp64()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp895 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
907 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
DPPCISelLowering.cpp1678 switch (ValVT.getSimpleVT().SimpleTy) { in LowerFormalArguments_SVR4()
1902 switch(ObjectVT.getSimpleVT().SimpleTy) { in LowerFormalArguments_Darwin()
2019 switch (ObjectVT.getSimpleVT().SimpleTy) { in LowerFormalArguments_Darwin()
3214 switch (Arg.getValueType().getSimpleVT().SimpleTy) { in LowerCall_Darwin()
3628 switch (Op.getValueType().getSimpleVT().SimpleTy) { in LowerFP_TO_INT()
/external/llvm/utils/TableGen/
DIntrinsicEmitter.cpp253 EmitTypeForValueType(OS, VVT.getVectorElementType().getSimpleVT().SimpleTy); in EmitTypeGenerate()
DCodeGenDAGPatterns.cpp514 VTOperand.MergeInTypeInfo(IVT.getSimpleVT().SimpleTy, TP); in EnforceVectorEltTypeIs()
529 if (EVT(TypeVec[i]).getVectorElementType().getSimpleVT().SimpleTy != VT) { in EnforceVectorEltTypeIs()
558 EEVT::TypeSet EltTypeSet(IVT.getSimpleVT().SimpleTy, TP); in EnforceVectorSubVectorTypeIs()
564 EEVT::TypeSet EltTypeSet(IVT.getSimpleVT().SimpleTy, TP); in EnforceVectorSubVectorTypeIs()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1099 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
1104 << RegVT.getSimpleVT().SimpleTy << "\n"; in LowerCCCArguments()

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