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Searched refs:UseMI (Results 1 – 25 of 29) sorted by relevance

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/external/llvm/lib/CodeGen/
DTwoAddressInstructionPass.cpp282 static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) { in isTwoAddrUse() argument
283 const MCInstrDesc &MCID = UseMI->getDesc(); in isTwoAddrUse()
285 MachineOperand &MO = UseMI->getOperand(i); in isTwoAddrUse()
287 (MO.isDef() || UseMI->isRegTiedToDefOperand(i))) in isTwoAddrUse()
306 MachineInstr *UseMI = UseMO.getParent(); in isProfitableToReMat() local
307 MachineBasicBlock *UseMBB = UseMI->getParent(); in isProfitableToReMat()
309 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); in isProfitableToReMat()
315 if (isTwoAddrUse(UseMI, Reg)) in isProfitableToReMat()
473 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg); in findOnlyInterestingUse() local
474 if (UseMI.getParent() != MBB) in findOnlyInterestingUse()
[all …]
DLiveRangeEdit.cpp167 MachineInstr *DefMI = 0, *UseMI = 0; in foldAsLoad() local
181 if (UseMI && UseMI != MI) in foldAsLoad()
186 UseMI = MI; in foldAsLoad()
189 if (!DefMI || !UseMI) in foldAsLoad()
193 << " into single use: " << *UseMI); in foldAsLoad()
196 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second) in foldAsLoad()
199 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI); in foldAsLoad()
203 LIS.ReplaceMachineInstrInMaps(UseMI, FoldMI); in foldAsLoad()
204 UseMI->eraseFromParent(); in foldAsLoad()
DPeepholeOptimizer.cpp166 MachineInstr *UseMI = &*UI; in OptimizeExtInstr() local
167 if (UseMI == MI) in OptimizeExtInstr()
170 if (UseMI->isPHI()) { in OptimizeExtInstr()
192 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) in OptimizeExtInstr()
195 MachineBasicBlock *UseMBB = UseMI->getParent(); in OptimizeExtInstr()
198 if (!LocalMIs.count(UseMI)) in OptimizeExtInstr()
238 MachineInstr *UseMI = UseMO->getParent(); in OptimizeExtInstr() local
239 MachineBasicBlock *UseMBB = UseMI->getParent(); in OptimizeExtInstr()
244 BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(), in OptimizeExtInstr()
DRegisterScavenging.cpp268 MachineBasicBlock::iterator &UseMI) { in findSurvivorReg() argument
325 UseMI = RestorePointMI; in findSurvivorReg()
354 MachineBasicBlock::iterator UseMI; in scavengeRegister() local
355 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister()
371 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) { in scavengeRegister()
380 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI); in scavengeRegister()
381 II = prior(UseMI); in scavengeRegister()
385 ScavengeRestore = prior(UseMI); in scavengeRegister()
DRegisterCoalescer.cpp573 MachineInstr *UseMI = &*UI; in RemoveCopyByCommutingDef() local
574 SlotIndex UseIdx = li_->getInstructionIndex(UseMI); in RemoveCopyByCommutingDef()
578 if (ULR->valno == AValNo && JoinedCopies.count(UseMI)) in RemoveCopyByCommutingDef()
616 MachineInstr *UseMI = &*UI; in RemoveCopyByCommutingDef() local
618 if (JoinedCopies.count(UseMI)) in RemoveCopyByCommutingDef()
620 if (UseMI->isDebugValue()) { in RemoveCopyByCommutingDef()
626 SlotIndex UseIdx = li_->getInstructionIndex(UseMI).getUseIndex(); in RemoveCopyByCommutingDef()
634 if (UseMI == CopyMI) in RemoveCopyByCommutingDef()
636 if (!UseMI->isCopy()) in RemoveCopyByCommutingDef()
638 if (UseMI->getOperand(0).getReg() != IntB.reg || in RemoveCopyByCommutingDef()
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DScheduleDAGInstrs.cpp312 MachineInstr *UseMI = UseSU->getInstr(); in BuildSchedGraph() local
313 const MCInstrDesc &UseMCID = UseMI->getDesc(); in BuildSchedGraph()
314 int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg); in BuildSchedGraph()
354 const MachineInstr *UseMI = UseMO->getParent(); in BuildSchedGraph() local
355 unsigned UseMOIdx = UseMO - &UseMI->getOperand(0); in BuildSchedGraph()
356 const MCInstrDesc &UseMCID = UseMI->getDesc(); in BuildSchedGraph()
364 if (UseMI->getParent() != MI->getParent()) { in BuildSchedGraph()
612 MachineInstr *UseMI = Use->getInstr(); in ComputeOperandLatency() local
615 if (UseMI) { in ComputeOperandLatency()
616 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) { in ComputeOperandLatency()
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DOptimizePHIs.cpp145 MachineInstr *UseMI = &*I; in IsDeadPHICycle() local
146 if (!UseMI->isPHI() || !IsDeadPHICycle(UseMI, PHIsInCycle)) in IsDeadPHICycle()
DDeadMachineInstructionElim.cpp146 MachineInstr *UseMI = Use.getParent(); in runOnMachineFunction() local
147 if (UseMI==MI) in runOnMachineFunction()
150 UseMI->getOperand(0).setReg(0U); in runOnMachineFunction()
DMachineSSAUpdater.cpp223 MachineInstr *UseMI = U.getParent(); in RewriteUse() local
225 if (UseMI->isPHI()) { in RewriteUse()
226 MachineBasicBlock *SourceBB = findCorrespondingPred(UseMI, &U); in RewriteUse()
229 NewVR = GetValueInMiddleOfBlock(UseMI->getParent()); in RewriteUse()
DMachineLICM.cpp769 MachineInstr *UseMI = &*UI; in HasAnyPHIUse() local
770 if (UseMI->isPHI()) in HasAnyPHIUse()
773 if (UseMI->isCopy()) { in HasAnyPHIUse()
774 unsigned Def = UseMI->getOperand(0).getReg(); in HasAnyPHIUse()
793 MachineInstr *UseMI = &*I; in HasHighOperandLatency() local
794 if (UseMI->isCopyLike()) in HasHighOperandLatency()
796 if (!CurLoop->contains(UseMI->getParent())) in HasHighOperandLatency()
798 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) { in HasHighOperandLatency()
799 const MachineOperand &MO = UseMI->getOperand(i); in HasHighOperandLatency()
806 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i)) in HasHighOperandLatency()
DTailDuplication.cpp245 MachineInstr *UseMI = &*UI; in TailDuplicateAndUpdate() local
247 if (UseMI->isDebugValue()) { in TailDuplicateAndUpdate()
252 UseMI->eraseFromParent(); in TailDuplicateAndUpdate()
255 if (UseMI->getParent() == DefBB && !UseMI->isPHI()) in TailDuplicateAndUpdate()
322 MachineInstr *UseMI = &*UI; in isDefLiveOut() local
323 if (UseMI->isDebugValue()) in isDefLiveOut()
325 if (UseMI->getParent() != BB) in isDefLiveOut()
DInlineSpiller.cpp208 MachineInstr *UseMI = 0; in isSnippet() local
229 if (UseMI && MI != UseMI) in isSnippet()
231 UseMI = MI; in isSnippet()
DLiveIntervalAnalysis.cpp752 MachineInstr *UseMI = I.skipInstruction();) { in shrinkToUses()
753 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg)) in shrinkToUses()
755 SlotIndex Idx = getInstructionIndex(UseMI).getUseIndex(); in shrinkToUses()
761 DEBUG(dbgs() << Idx << '\t' << *UseMI in shrinkToUses()
983 MachineInstr *UseMI = &*ri; in isReMaterializable() local
984 SlotIndex UseIdx = getInstructionIndex(UseMI); in isReMaterializable()
DRegAllocFast.cpp553 const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg); in defineVirtReg() local
555 if (UseMI.isCopyLike()) in defineVirtReg()
556 Hint = UseMI.getOperand(0).getReg(); in defineVirtReg()
/external/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp121 MachineInstr *UseMI = &*MRI->use_nodbg_begin(Reg); in getDefReg() local
122 if (UseMI->getParent() != MBB) in getDefReg()
125 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()
126 Reg = UseMI->getOperand(0).getReg(); in getDefReg()
130 UseMI = &*MRI->use_nodbg_begin(Reg); in getDefReg()
131 if (UseMI->getParent() != MBB) in getDefReg()
DARMBaseInstrInfo.cpp1702 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI, in FoldImmediate() argument
1716 unsigned UseOpc = UseMI->getOpcode(); in FoldImmediate()
1731 Commute = UseMI->getOperand(2).getReg() != Reg; in FoldImmediate()
1783 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); in FoldImmediate()
1784 bool isKill = UseMI->getOperand(OpIdx).isKill(); in FoldImmediate()
1786 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(), in FoldImmediate()
1787 *UseMI, UseMI->getDebugLoc(), in FoldImmediate()
1791 UseMI->setDesc(get(NewUseOpc)); in FoldImmediate()
1792 UseMI->getOperand(1).setReg(NewReg); in FoldImmediate()
1793 UseMI->getOperand(1).setIsKill(); in FoldImmediate()
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DARMBaseInstrInfo.h335 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
344 const MachineInstr *UseMI, unsigned UseIdx) const;
381 const MachineInstr *UseMI, unsigned UseIdx) const;
DThumb2InstrInfo.h60 void scheduleTwoAddrSource(MachineInstr *SrcMI, MachineInstr *UseMI,
DThumb1RegisterInfo.h61 MachineBasicBlock::iterator &UseMI,
DThumb1RegisterInfo.cpp557 MachineBasicBlock::iterator &UseMI, in saveScavengerRegister() argument
574 for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) { in saveScavengerRegister()
584 UseMI = II; in saveScavengerRegister()
591 AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)). in saveScavengerRegister()
DThumb2InstrInfo.cpp566 MachineInstr *UseMI, in scheduleTwoAddrSource() argument
572 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg); in scheduleTwoAddrSource()
580 MachineBasicBlock *MBB = UseMI->getParent(); in scheduleTwoAddrSource()
/external/llvm/lib/Target/
DTargetInstrInfo.cpp67 const MachineInstr *UseMI, unsigned UseIdx) const { in getOperandLatency() argument
72 unsigned UseClass = UseMI->getDesc().getSchedClass(); in getOperandLatency()
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h190 MachineInstr *UseMI, in scheduleTwoAddrSource() argument
610 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, in FoldImmediate() argument
635 const MachineInstr *UseMI, unsigned UseIdx) const;
664 const MachineInstr *UseMI, unsigned UseIdx) const { in hasHighOperandLatency() argument
DTargetRegisterInfo.h683 MachineBasicBlock::iterator &UseMI, in saveScavengerRegister() argument
/external/llvm/include/llvm/CodeGen/
DRegisterScavenging.h162 MachineBasicBlock::iterator &UseMI);

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