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Searched refs:VTRN (Results 1 – 10 of 10) sorted by relevance

/external/llvm/test/CodeGen/ARM/
Dvuzp.ll27 ; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
Dvzip.ll27 ; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
Dvtrn.ll99 ; Undef shuffle indices should not prevent matching to VTRN:
/external/llvm/lib/Target/ARM/
DARMISelLowering.h155 VTRN, // transpose enumerator
DARMISelLowering.cpp903 case ARMISD::VTRN: return "ARMISD::VTRN"; in getTargetNodeName()
4251 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
4332 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
4342 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
DARMISelDAGToDAG.cpp2499 case ARMISD::VTRN: { in Select()
DARMInstrNEON.td111 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
1785 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
4723 // VTRN : Vector Transpose
/external/clang/include/clang/Basic/
Darm_neon.td386 def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
/external/valgrind/main/none/tests/arm/
Dneon128.stdout.exp2127 ---- VTRN ----
Dneon64.stdout.exp3376 ---- VTRN ----