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/external/llvm/test/CodeGen/X86/
Dvshift-3.ll6 ; Note that x86 does have ashr
13 %ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
14 store <2 x i64> %ashr, <2 x i64>* %dst
22 %ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
23 store <4 x i32> %ashr, <4 x i32>* %dst
36 %ashr = ashr <4 x i32> %val, %3
37 store <4 x i32> %ashr, <4 x i32>* %dst
45 %ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
46 store <8 x i16> %ashr, <8 x i16>* %dst
64 %ashr = ashr <8 x i16> %val, %7
[all …]
Dfield-extract-use-trunc.ll13 %tmp7.25 = ashr i32 %f11, 24
19 %tmp7.25 = ashr i32 %f11, 24
25 %tmp7.25 = ashr i64 %f11, 32
31 %tmp7.25 = ashr i16 %f11, 8
37 %tmp7.25 = ashr i16 %f11, 8
D2008-05-12-tailmerge-5.ll51 %tmp17 = ashr i32 %tmp16, 23 ; <i32> [#uses=1]
54 %sextr = ashr i16 %sextl, 7 ; <i16> [#uses=2]
56 %sextr20 = ashr i16 %sextl19, 7 ; <i16> [#uses=0]
58 %sextr22 = ashr i16 %sextl21, 7 ; <i16> [#uses=1]
87 %tmp39 = ashr i16 %tmp38, 7 ; <i16> [#uses=1]
89 %sextr41 = ashr i16 %sextl40, 7 ; <i16> [#uses=2]
91 %sextr43 = ashr i16 %sextl42, 7 ; <i16> [#uses=0]
93 %sextr45 = ashr i16 %sextl44, 7 ; <i16> [#uses=1]
108 %tmp55 = ashr i16 %tmp54, 7 ; <i16> [#uses=1]
110 %sextr57 = ashr i16 %sextl56, 7 ; <i16> [#uses=2]
[all …]
/external/llvm/test/CodeGen/XCore/
Dashr.ll2 define i32 @ashr(i32 %a, i32 %b) {
3 %1 = ashr i32 %a, %b
6 ; CHECK: ashr:
7 ; CHECK-NEXT: ashr r0, r0, r1
10 %1 = ashr i32 %a, 24
14 ; CHECK-NEXT: ashr r0, r0, 24
17 %1 = ashr i32 %a, 31
21 ; CHECK-NEXT: ashr r0, r0, 32
32 ; CHECK-NEXT: ashr r0, r0, 32
44 ; CHECK-NEXT: ashr r0, r0, 32
[all …]
/external/llvm/test/Transforms/InstCombine/
Dshift-sra.ll7 %Y = ashr i32 %X, %shift.upgrd.1 ; <i32> [#uses=1]
17 %tmp5 = ashr i32 %tmp4, 3 ; <i32> [#uses=1]
29 %Y2 = ashr i64 %Y, 63
33 %S = ashr i64 %P, 12
47 %Y2 = ashr i64 %Y, 63
52 %S = ashr i64 %R, 12
71 %S = ashr i32 %P, 16
75 ; CHECK-NEXT: ashr i32 %P, 16
Dsignext.ll12 ; CHECK: %tmp.3 = ashr exact i32 %sext, 16
23 ; CHECK: %tmp.3 = ashr exact i32 %sext, 16
54 ; CHECK: %tmp.3 = ashr exact i32 %sext, 24
60 %tmp.4 = ashr i32 %tmp.2, 16 ; <i32> [#uses=1]
64 ; CHECK: %tmp.4 = ashr exact i32 %tmp.2, 16
71 %tmp.5 = ashr i32 %sext1, 16 ; <i32> [#uses=1]
85 ; CHECK: %shr = ashr i32 %x, 5
D2009-03-20-AShrOverShift.ll1 ; RUN: opt < %s -instcombine -S | grep {ashr i32 %val, 31}
6 %shr = ashr i32 %val, 15 ; <i32> [#uses=3]
7 %shr4 = ashr i32 %shr, 17 ; <i32> [#uses=1]
Dapint-shift.ll18 %B = ashr i41 %A, 0 ; <i41> [#uses=1]
24 %B = ashr i39 0, %A ; <i39> [#uses=1]
46 %B = ashr i29 -1, %A ; <i29> [#uses=1]
76 %B = ashr i47 %A, 8 ; <i47> [#uses=1]
83 %B = ashr i18 %a, 8 ; <i18> [#uses=1]
116 %tmp.3 = ashr i84 %X, 4 ; <i84> [#uses=1]
135 %B = ashr i37 %A, 2 ; <i37> [#uses=1]
141 %B = ashr i39 %A, 2 ; <i39> [#uses=1]
147 %B = ashr i13 %A, 12 ; <i13> [#uses=1]
166 %C = ashr i44 %B, 33 ; <i44> [#uses=1]
D2007-03-26-BadShiftMask.ll3 ; RUN: grep {ashr exact i32 %.mp137, 2}
15 %tmp136 = ashr i32 %b8, 1 ; <i32> [#uses=1]
17 %tmp139 = ashr i32 %tmp134, 2 ; <i32> [#uses=1]
19 %tmp143 = ashr i32 %tmp137, 2 ; <i32> [#uses=1]
Dapint-shift-simplify.ll2 ; RUN: egrep {shl|lshr|ashr} | count 3
19 %X = ashr i49 %A, %C
20 %Y = ashr i49 %B, %C
Dexact.ll11 ; CHECK: ashr exact i32 %x, 3
72 ; CHECK: %B = ashr exact i64 %A, 2
76 %B = ashr i64 %A, 2 ; X/4
85 %A = ashr exact i64 %X, 2 ; X/4
94 %Y = ashr exact i64 %X, 2 ; x / 4
100 ; Make sure we don't transform the ashr here into an sdiv
108 %X = ashr exact i32 %W, 31
Didioms.ll18 %d = ashr i32 %not, %b
23 %e = ashr i32 %a, %b
30 ; CHECK: %f = ashr i32 %a, %b
Dshift.ll23 %B = ashr i32 %A, 0 ; <i32> [#uses=1]
31 %B = ashr i32 0, %shift.upgrd.2 ; <i32> [#uses=1]
53 %B = ashr i32 undef, 2 ;; top two bits must be equal, so not undef
60 %B = ashr i32 undef, %A ;; top %A bits must be equal, so not undef
77 %B = ashr i32 -1, %shift.upgrd.3 ;; Always equal to -1
127 %B = ashr i32 %A, 8 ; <i32> [#uses=1]
139 %B = ashr i8 %a, 3 ; <i8> [#uses=1]
191 %tmp.3 = ashr i32 %X, 4
222 %B = ashr i32 %A, 2 ; <i32> [#uses=1]
234 %B = ashr i32 %A, 2 ; <i32> [#uses=1]
[all …]
Dashr-nop.ll1 ; RUN: opt < %s -instcombine -S | not grep ashr
6 %t = ashr i32 %n, 17
/external/llvm/test/CodeGen/CBackend/
Dpr2408.ll6 %shr = ashr i32 %a, 0 ; <i32> [#uses=1]
7 %shr2 = ashr i32 2, 0 ; <i32> [#uses=1]
9 %shr4 = ashr i32 2, 0 ; <i32> [#uses=1]
/external/llvm/test/CodeGen/ARM/
Dsmul.ll13 %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1]
21 %tmp1 = ashr i32 %x, 16 ; <i32> [#uses=1]
22 %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1]
31 %tmp2 = ashr i32 %y, 16 ; <i32> [#uses=1]
D2010-05-21-BuildVector.ll10 %4 = ashr i32 %3, 30
17 %8 = ashr i32 %7, 30
24 %12 = ashr i32 %11, 30
31 %16 = ashr i32 %15, 30
Dsbfx.ll8 %tmp2 = ashr i32 %tmp, 12
26 %tmp2 = ashr i32 %tmp, 29
45 %tmp2 = ashr i32 %tmp, 1
Dvshift.ll296 %tmp3 = ashr <8 x i8> %tmp1, %tmp2
306 %tmp3 = ashr <4 x i16> %tmp1, %tmp2
316 %tmp3 = ashr <2 x i32> %tmp1, %tmp2
326 %tmp3 = ashr <1 x i64> %tmp1, %tmp2
334 %tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
342 %tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
350 %tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 >
358 %tmp2 = ashr <1 x i64> %tmp1, < i64 64 >
368 %tmp3 = ashr <16 x i8> %tmp1, %tmp2
378 %tmp3 = ashr <8 x i16> %tmp1, %tmp2
[all …]
/external/llvm/test/CodeGen/SystemZ/
D04-RetShifts.ll11 %shr = ashr i32 %a, %add ; <i32> [#uses=1]
32 %shr = ashr i64 %a, %add ; <i64> [#uses=1]
52 %shr = ashr i32 %a, 1
70 %shr = ashr i32 %a, %idx
88 %shr = ashr i64 %a, 1
106 %shr = ashr i64 %a, %idx
/external/llvm/test/ExecutionEngine/
Dtest-shift.ll14 %tr1.s = ashr i32 1, %shift.upgrd.5 ; <i32> [#uses=0]
15 %tr2.s = ashr i32 1, 4 ; <i32> [#uses=0]
19 %tr1.l = ashr i64 1, 4 ; <i64> [#uses=0]
21 %tr2.l = ashr i64 1, %shift.upgrd.7 ; <i64> [#uses=0]
/external/llvm/test/CodeGen/PowerPC/
Drlwimi-keep-rsh.ll13 %tmp0 = ashr i32 %d, 31
16 %tmp3 = ashr i32 %b, 31
17 %tmp4 = ashr i32 %a, 4
Dand_sra.ll6 %tmp.80 = ashr i32 %tmp.79, 15 ; <i32> [#uses=1]
13 %tmp.80 = ashr i32 %tmp.79, 15 ; <i32> [#uses=1]
21 %tmp.2540 = ashr i32 %specbits.6.1, 11 ; <i32> [#uses=1]
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-smul.ll12 %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1]
20 %tmp1 = ashr i32 %x, 16 ; <i32> [#uses=1]
21 %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1]
/external/llvm/test/CodeGen/PTX/
Dshr.ll26 %z = ashr i32 %x, %y
33 %z = ashr i32 %x, 3
40 %z = ashr i32 -3, %x

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