| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 184 def VADDD : ADbI<0b11100, 0b11, 0, 0,
189 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
198 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
203 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
258 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
263 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
273 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
278 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
292 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
297 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
[all …]
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| D | ARMInstrNEON.td | 1787 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1793 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2576 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2579 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2684 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2687 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2698 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2701 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3576 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3589 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
[all …]
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| D | ARMInstrThumb.td | 220 T1Disassembly<0b11, 0x00>; // A8.6.110
224 T1Disassembly<0b11, 0x10>; // A8.6.410
228 T1Disassembly<0b11, 0x20>; // A8.6.408
232 T1Disassembly<0b11, 0x30>; // A8.6.409
236 T1Disassembly<0b11, 0x40>; // A8.6.157
392 def tBL : TIx2<0b11110, 0b11, 1,
405 def tBLXi : TIx2<0b11110, 0b11, 0,
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| D | ARMInstrThumb2.td | 1985 defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2356 let Inst{5-4} = 0b11;
2438 let Inst{5-4} = 0b11;
2593 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2607 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2787 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2881 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2918 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
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| D | ARMInstrInfo.td | 2043 let Inst{24-23} = 0b11; // Increment Before
2051 let Inst{24-23} = 0b11; // Increment Before
2918 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2930 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2961 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
3005 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
3453 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3465 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
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| D | ARMInstrFormats.td | 1918 let Inst{24-23} = 0b11;
1919 let Inst{21-20} = 0b11;
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| /external/libvpx/vp8/encoder/x86/ |
| D | fwalsh_sse2.asm | 79 pmaddwd xmm2, [GLOBAL(cn1)] ; c11 b11 c10 b10
85 pshufd xmm5, xmm2, 0xd8 ; c11 c10 b11 b10
90 punpcklqdq xmm0, xmm5 ; b11 b10 a11 a10
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| /external/clang/test/SemaCXX/ |
| D | constant-expression.cpp | 45 b11 : true? 1 + cval * Struct::sval ^ itval / (int)1.5 - sizeof(Struct) : 0
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| /external/clang/lib/Headers/ |
| D | avxintrin.h | 935 char b11, char b10, char b09, char b08, in _mm256_set_epi8() argument
941 b08, b09, b10, b11, b12, b13, b14, b15, in _mm256_set_epi8()
990 char b11, char b10, char b09, char b08, in _mm256_setr_epi8() argument
997 b15, b14, b13, b12, b11, b10, b09, b08, in _mm256_setr_epi8()
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| D | emmintrin.h | 1054 _mm_set_epi8(char b15, char b14, char b13, char b12, char b11, char b10, char b9, char b8, char b7,… in _mm_set_epi8() argument
1056 return (__m128i)(__v16qi){ b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15 }; in _mm_set_epi8()
1108 …r b3, char b4, char b5, char b6, char b7, char b8, char b9, char b10, char b11, char b12, char b13… in _mm_setr_epi8() argument
1110 return (__m128i)(__v16qi){ b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15 }; in _mm_setr_epi8()
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| /external/webp/src/enc/ |
| D | dsp_sse2.c | 360 const __m128i b11 = _mm_unpackhi_epi64(b01, b01); in FTransformSSE2() local
365 const __m128i e0 = _mm_add_epi16(b01, b11); in FTransformSSE2()
366 const __m128i e2 = _mm_sub_epi16(b01, b11); in FTransformSSE2()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFormats.td | 180 let Inst{5-4} = 0b11;
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| /external/valgrind/main/VEX/priv/ |
| D | guest_ppc_toIR.c | 5529 UChar b11 = toUChar( IFIELD( theInstr, 11, 1 ) ); in dis_proc_ctl() local
5579 if (b20 == 1 && b11 == 0) { in dis_proc_ctl()
5701 if (b11 != 0) in dis_proc_ctl()
7102 UChar b11 = toUChar( IFIELD( theInstr, 11, 1 ) ); in dis_fp_scr() local
7104 if (b16to22 != 0 || b11 != 0) { in dis_fp_scr()
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUInstrInfo.td | 3437 def BISLED_00: BISLEDForm<0b11, "bisled\t$$lr, $func", [/* empty pattern */]>;
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| /external/webkit/PerformanceTests/Parser/resources/ |
| D | final-url-en | 48972 http://www.imakenews.com/psaanews/index000050690.cfm?x=b11,0,w
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