Home
last modified time | relevance | path

Searched refs:getSimpleVT (Results 1 – 25 of 35) sorted by relevance

12

/external/llvm/include/llvm/Target/
DTargetLowering.h183 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; in getRegClassFor()
195 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy]; in getRepRegClassFor()
203 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy]; in getRepRegClassCostFor()
211 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); in isTypeLegal()
212 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; in isTypeLegal()
230 unsigned I = VT.getSimpleVT().SimpleTy; in setTypeAction()
352 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; in getOperationAction()
378 VT.getSimpleVT() < MVT::LAST_VALUETYPE && in getLoadExtAction()
380 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; in getLoadExtAction()
394 assert(ValVT.getSimpleVT() < MVT::LAST_VALUETYPE && in getTruncStoreAction()
[all …]
DTargetCallingConv.h115 VT = vt.getSimpleVT(); in InputArg()
133 VT = vt.getSimpleVT(); in OutputArg()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp112 MVT VT = RealVT.getSimpleVT(); in getRegForValue()
116 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); in getRegForValue()
191 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeRegForValue()
269 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, in getRegForGEPIndex()
274 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, in getRegForGEPIndex()
346 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, in SelectBinaryOp()
348 VT.getSimpleVT()); in SelectBinaryOp()
375 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, in SelectBinaryOp()
376 Op0IsKill, Imm, VT.getSimpleVT()); in SelectBinaryOp()
386 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), in SelectBinaryOp()
[all …]
DSelectionDAG.cpp64 switch (VT.getSimpleVT().SimpleTy) { in EVTToAPFloatSemantics()
635 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0; in RemoveNodeFromCSEMaps()
636 ValueTypeNodes[VT.getSimpleVT().SimpleTy] = 0; in RemoveNodeFromCSEMaps()
1162 if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >= in getValueType()
1164 ValueTypeNodes.resize(VT.getSimpleVT().SimpleTy+1); in getValueType()
1167 ExtendedValueTypeNodes[VT] : ValueTypeNodes[VT.getSimpleVT().SimpleTy]; in getValueType()
2910 assert(VT.getSimpleVT() <= N1.getValueType().getSimpleVT() && in getNode()
2921 if (VT.getSimpleVT() == N1.getValueType().getSimpleVT()) in getNode()
3130 assert(N2.getValueType().getSimpleVT() <= N1.getValueType().getSimpleVT() && in getNode()
3140 if (VT.getSimpleVT() == N2.getValueType().getSimpleVT()) in getNode()
[all …]
DLegalizeDAG.cpp362 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP()
2271 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in ExpandFPLibCall()
2288 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in ExpandIntLibCall()
2303 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in isDivRemLibcallAvailable()
2348 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { in ExpandDivRemLibCall()
2571 switch (Op0.getValueType().getSimpleVT().SimpleTy) { in ExpandLegalINT_TO_FP()
2618 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); in PromoteLegalINT_TO_FP()
2660 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); in PromoteLegalFP_TO_INT()
2691 switch (VT.getSimpleVT().SimpleTy) { in ExpandBSWAP()
2836 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); in ExpandAtomic()
/external/llvm/lib/Target/PTX/
DPTXISelDAGToDAG.cpp102 R2 = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT()); in SelectADDRrr()
119 Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT()); in SelectADDRri()
155 Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT()); in SelectADDRii()
DPTXISelLowering.cpp177 PtrVT.getSimpleVT(), in LowerGlobalAddress()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp153 VT = evt.getSimpleVT(); in isTypeLegal()
180 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitLoad()
237 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
275 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
310 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, in X86FastEmitExtend()
758 SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, in X86SelectRet()
800 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode()
815 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode()
960 ResultReg = FastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, in X86SelectZExt()
1684 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT(), in DoSelectCall()
[all …]
DX86ISelDAGToDAG.cpp1382 switch (NVT.getSimpleVT().SimpleTy) { in SelectAtomicLoadAdd()
1594 switch (NVT.getSimpleVT().SimpleTy) { in SelectAtomicLoadArith()
1798 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1834 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1862 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1870 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1880 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1962 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1970 switch (NVT.getSimpleVT().SimpleTy) { in Select()
1981 switch (NVT.getSimpleVT().SimpleTy) { in Select()
[all …]
DX86ISelLowering.cpp876 VT.getSimpleVT().SimpleTy, Custom); in X86TargetLowering()
878 VT.getSimpleVT().SimpleTy, Custom); in X86TargetLowering()
880 VT.getSimpleVT().SimpleTy, Custom); in X86TargetLowering()
1280 switch (VT.getSimpleVT().SimpleTy) { in findRepresentativeClass()
5212 switch (VT.getSimpleVT().SimpleTy) { in RewriteAsNarrowerShuffle()
5633 switch(VT.getSimpleVT().SimpleTy) { in getUNPCKLOpcode()
5651 switch(VT.getSimpleVT().SimpleTy) { in getUNPCKHOpcode()
6282 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && in LowerSCALAR_TO_VECTOR()
6743 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && in LowerSINT_TO_FP()
7056 assert(DstTy.getSimpleVT() <= MVT::i64 && in FP_TO_INTHelper()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430ISelDAGToDAG.cpp309 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
334 MVT VT = LD->getMemoryVT().getSimpleVT(); in SelectIndexedLoad()
363 MVT VT = LD->getMemoryVT().getSimpleVT(); in SelectIndexedBinOp()
DMSP430ISelLowering.cpp326 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
331 << RegVT.getSimpleVT().SimpleTy << "\n"; in LowerCCCArguments()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp98 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); in addTypeForNEON()
99 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(), in addTypeForNEON()
100 PromotedLdStVT.getSimpleVT()); in addTypeForNEON()
102 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); in addTypeForNEON()
103 AddPromotedToType (ISD::STORE, VT.getSimpleVT(), in addTypeForNEON()
104 PromotedLdStVT.getSimpleVT()); in addTypeForNEON()
109 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom); in addTypeForNEON()
110 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); in addTypeForNEON()
112 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); in addTypeForNEON()
113 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); in addTypeForNEON()
[all …]
DARMFastISel.cpp681 VT = evt.getSimpleVT(); in isTypeLegal()
827 switch (VT.getSimpleVT().SimpleTy) { in ARMSimplifyAddress()
874 if (VT.getSimpleVT().SimpleTy == MVT::f32 || in AddLoadStoreOperands()
875 VT.getSimpleVT().SimpleTy == MVT::f64) in AddLoadStoreOperands()
892 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0); in AddLoadStoreOperands()
901 if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0); in AddLoadStoreOperands()
913 switch (VT.getSimpleVT().SimpleTy) { in ARMEmitLoad()
966 switch (VT.getSimpleVT().SimpleTy) { in ARMEmitStore()
1496 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, in FastEmitExtend()
2002 switch (SrcVT.getSimpleVT().SimpleTy) { in SelectIntCast()
DARMISelDAGToDAG.cpp1318 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectT2IndexedLoad()
1472 switch (VT.getSimpleVT().SimpleTy) { in SelectVLD()
1600 switch (VT.getSimpleVT().SimpleTy) { in SelectVST()
1754 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDSTLane()
1867 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDDup()
2183 switch (VT.getSimpleVT().SimpleTy) { in SelectCMOVOp()
2464 switch (VT.getSimpleVT().SimpleTy) { in Select()
2483 switch (VT.getSimpleVT().SimpleTy) { in Select()
2502 switch (VT.getSimpleVT().SimpleTy) { in Select()
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp504 switch(VT.getSimpleVT().SimpleTy){ in getSetCCResultType()
1137 switch (ObjectVT.getSimpleVT().SimpleTy) { in LowerFormalArguments()
1304 switch (Arg.getValueType().getSimpleVT().SimpleTy) { in LowerCall()
1660 switch (VT.getSimpleVT().SimpleTy) { in LowerBUILD_VECTOR()
1953 switch (Op.getValueType().getSimpleVT().SimpleTy) { in LowerSCALAR_TO_VECTOR()
1972 switch (Op0.getValueType().getSimpleVT().SimpleTy) { in LowerSCALAR_TO_VECTOR()
2017 switch (VT.getSimpleVT().SimpleTy) { in LowerEXTRACT_VECTOR_ELT()
2109 switch (VT.getSimpleVT().SimpleTy) { in LowerEXTRACT_VECTOR_ELT()
2351 switch (VT.getSimpleVT().SimpleTy) { in LowerCTPOP()
2670 MVT simpleVT = VT.getSimpleVT(); in LowerTRUNCATE()
[all …]
DSPUISelDAGToDAG.cpp83 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) { in isIntS16Immediate()
660 switch (Op0VT.getSimpleVT().SimpleTy) { in Select()
852 getRC( VT.getSimpleVT()), Chain); in Select()
/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp610 switch (NVT.getSimpleVT().SimpleTy) { in Select()
690 switch (NVT.getSimpleVT().SimpleTy) { in Select()
DSystemZISelLowering.cpp310 switch (LocVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
314 << LocVT.getSimpleVT().SimpleTy in LowerCCCArguments()
/external/llvm/include/llvm/CodeGen/
DValueTypes.h547 MVT getSimpleVT() const { in getSimpleVT() function
/external/llvm/lib/Target/Mips/
DMipsISelDAGToDAG.cpp189 N->getValueType(0).getSimpleVT().SimpleTy; in SelectLoadFp64()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp895 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
907 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
/external/llvm/utils/TableGen/
DIntrinsicEmitter.cpp253 EmitTypeForValueType(OS, VVT.getVectorElementType().getSimpleVT().SimpleTy); in EmitTypeGenerate()
DCodeGenDAGPatterns.cpp514 VTOperand.MergeInTypeInfo(IVT.getSimpleVT().SimpleTy, TP); in EnforceVectorEltTypeIs()
529 if (EVT(TypeVec[i]).getVectorElementType().getSimpleVT().SimpleTy != VT) { in EnforceVectorEltTypeIs()
558 EEVT::TypeSet EltTypeSet(IVT.getSimpleVT().SimpleTy, TP); in EnforceVectorSubVectorTypeIs()
564 EEVT::TypeSet EltTypeSet(IVT.getSimpleVT().SimpleTy, TP); in EnforceVectorSubVectorTypeIs()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1099 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
1104 << RegVT.getSimpleVT().SimpleTy << "\n"; in LowerCCCArguments()

12