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/external/webkit/LayoutTests/storage/domstorage/localstorage/
Ddelete-removal-expected.txt5 foo (after an indexed setter set) is: bar
12 foo (after an indexed delete) is: undefined
/external/webkit/LayoutTests/storage/domstorage/sessionstorage/
Ddelete-removal-expected.txt5 foo (after an indexed setter set) is: bar
12 foo (after an indexed delete) is: undefined
/external/llvm/test/MC/ARM/
Darm_addrmode2.s3 @ Post-indexed
29 @ Pre-indexed
/external/e2fsprogs/tests/f_dup_de2/
Dname1 duplicate directory entries for non-indexed dirs
/external/llvm/test/CodeGen/ARM/
Ddyn-stackalloc.ll41 %tmp6.indexed = getelementptr i8* %tmp6, i32 %tmp6.len
42 …call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp6.indexed, i8* getelementptr inbounds ([2 x i8]* @str…
/external/webkit/LayoutTests/fast/encoding/
Dcss-charset-expected.txt3 Test that @charset works and that indexed rule access via an IE-specific rules property does not ta…
/external/skia/gpu/src/
DGrGpuGLFixed.cpp262 bool indexed = NULL != startIndex; in setupGeometry() local
266 setBuffers(indexed, &extraVertexOffset, &extraIndexOffset); in setupGeometry()
277 if (indexed) { in setupGeometry()
DGrGpuGL.h112 void setBuffers(bool indexed,
DGrGpuGLShaders.cpp623 bool indexed = NULL != startIndex; in setupGeometry() local
627 setBuffers(indexed, &extraVertexOffset, &extraIndexOffset); in setupGeometry()
641 if (indexed) { in setupGeometry()
DGrGpuGL.cpp2012 void GrGpuGL::setBuffers(bool indexed, in setBuffers() argument
2043 if (indexed) { in setBuffers()
/external/llvm/test/CodeGen/Thumb/
Ddyn-stackalloc.ll62 %tmp6.indexed = getelementptr i8* %tmp6, i32 %tmp6.len
63 …call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp6.indexed, i8* getelementptr inbounds ([2 x i8]* @str…
/external/webkit/LayoutTests/fast/dom/NodeList/
Dnodelist-item-assignment-expected.txt1 This tests that indexed assignments to items of a NodeList do not override original values. See htt…
/external/llvm/test/Assembler/
Dgetelementptr.ll3 ; Verify that over-indexed getelementptrs are folded.
/external/llvm/lib/Target/ARM/
DREADME.txt278 Pre-/post- indexed load / stores:
280 1) We should not make the pre/post- indexed load/store transform if the base ptr
301 2) Consider spliting a indexed load / store into a pair of add/sub + load/store
304 3) Enhance LSR to generate more opportunities for indexed ops.
306 4) Once we added support for multiple result patterns, write indexed loads
309 5) Use VLDM / VSTM to emulate indexed FP load / store.
408 1. Teach LSR about pre- and post- indexed ops to allow iv increment be merged
DARMInstrFormats.td657 // Pre-indexed stores
685 // Post-indexed stores
1183 // T2Iidxldst - Thumb2 indexed load / store instructions.
1202 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
/external/sonivox/arm-hybrid-22k/lib_src/
DARM_synth_constants_gnu.inc56 @ if the OUTPUT PCM sample is 16-bits, then when using indexed addressing,
/external/sonivox/arm-wt-22k/lib_src/
DARM_synth_constants_gnu.inc56 @ if the OUTPUT PCM sample is 16-bits, then when using indexed addressing,
/external/chromium/chrome/browser/history/
Dhistory_indexer.idl17 // page to be indexed. The html content and thumbnail for the same url
/external/openssl/crypto/rc2/
Drrc2.doc111 In addition the fifth and eleventh rounds add the contents of the S-box indexed
135 indexed by one of the data words from another one of the data words following
/external/e2fsprogs/debugfs/
Ddebug_cmds.ct139 request do_htree_dump, "Dump a hash-indexed directory",
/external/llvm/bindings/ocaml/target/
Dllvm_target.mli99 (** Computes the byte offset of the indexed struct element for a target.
/external/icu4c/samples/legacy/
DREADME6 What is it all about: Let's say you have a 10 Tb database indexed using ICU 1.8.1. sortkeys. New IC…
/external/llvm/docs/HistoricalNotes/
D2003-06-25-Reoptimizer1.txt13 counters in a map indexed by return address. If the trigger count
/external/mesa3d/docs/
DlibGL.txt125 functions are kept in an array, indexed by screen number, in the
/external/oprofile/events/ppc64/cell-be/
Devents66 …dges minimum:10000 name:larx_miss_th1 : Load word and reserve indexed (lwarx/ldarx) for…
67 …ges minimum:10000 name:stcx_miss_th1 : Store word conditional indexed (stwcx/stdcx) for…
88 …:PPU_02_edges minimum:10000 name:larx_miss : Load and reserve indexed (lwarx/ldarx) for…
89 …02_edges minimum:10000 name:stcx_miss_th2 : Store conditional indexed (stwcx/stdcx) for…

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