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/external/mesa3d/src/glsl/
Dir_variable.cpp35 const glsl_type *type, exec_list *instructions, in add_variable() argument
60 instructions->push_tail(var); in add_variable()
67 add_uniform(exec_list *instructions, in add_uniform() argument
71 return add_variable(name, ir_var_uniform, -1, type, instructions, in add_uniform()
76 add_builtin_variable(const builtin_variable *proto, exec_list *instructions, in add_builtin_variable() argument
86 add_variable(proto->name, proto->mode, proto->slot, type, instructions, in add_builtin_variable()
91 add_builtin_constant(exec_list *instructions, in add_builtin_constant() argument
97 instructions, state->symbols); in add_builtin_constant()
105 generate_100ES_uniforms(exec_list *instructions, in generate_100ES_uniforms() argument
108 add_builtin_constant(instructions, state, "gl_MaxVertexAttribs", in generate_100ES_uniforms()
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Dir_optimization.h41 bool do_algebraic(exec_list *instructions);
42 bool do_constant_folding(exec_list *instructions);
43 bool do_constant_variable(exec_list *instructions);
44 bool do_constant_variable_unlinked(exec_list *instructions);
45 bool do_copy_propagation(exec_list *instructions);
46 bool do_constant_propagation(exec_list *instructions);
47 bool do_dead_code(exec_list *instructions);
48 bool do_dead_code_local(exec_list *instructions);
49 bool do_dead_code_unlinked(exec_list *instructions);
50 bool do_dead_functions(exec_list *instructions);
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Dast_to_hir.cpp60 _mesa_ast_to_hir(exec_list *instructions, struct _mesa_glsl_parse_state *state) in _mesa_ast_to_hir() argument
62 _mesa_glsl_initialize_variables(instructions, state); in _mesa_ast_to_hir()
63 _mesa_glsl_initialize_functions(instructions, state); in _mesa_ast_to_hir()
85 ast->hir(instructions, state); in _mesa_ast_to_hir()
637 do_assignment(exec_list *instructions, struct _mesa_glsl_parse_state *state, in do_assignment() argument
703 instructions->push_tail(var); in do_assignment()
704 instructions->push_tail(new(ctx) ir_assignment(deref_var, in do_assignment()
710 instructions->push_tail(new(ctx) ir_assignment(lhs, deref_var, NULL)); in do_assignment()
716 get_lvalue_copy(exec_list *instructions, ir_rvalue *lvalue) in get_lvalue_copy() argument
723 instructions->push_tail(var); in get_lvalue_copy()
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Dast_function.cpp38 process_parameters(exec_list *instructions, exec_list *actual_parameters, in process_parameters() argument
46 ir_rvalue *result = ast->hir(instructions, state); in process_parameters()
96 match_function_by_name(exec_list *instructions, const char *name, in match_function_by_name() argument
122 emit_function(state, instructions, f); in match_function_by_name()
179 instructions->push_tail(var); in match_function_by_name()
183 instructions->push_tail(assign); in match_function_by_name()
190 instructions->push_tail(call); in match_function_by_name()
334 process_array_constructor(exec_list *instructions, in process_array_constructor() argument
362 process_parameters(instructions, &actual_parameters, parameters, state); in process_array_constructor()
427 instructions->push_tail(var); in process_array_constructor()
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Dopt_discard_simplification.cpp103 find_unconditional_discard(exec_list &instructions) in find_unconditional_discard() argument
105 foreach_list(n, &instructions) { in find_unconditional_discard()
165 do_discard_simplification(exec_list *instructions) in do_discard_simplification() argument
168 ir_discard *discard = find_unconditional_discard(*instructions); in do_discard_simplification()
170 instructions->make_empty(); in do_discard_simplification()
171 instructions->push_tail(discard); in do_discard_simplification()
177 visit_list_elements(&v, instructions); in do_discard_simplification()
Dast.h79 virtual ir_rvalue *hir(exec_list *instructions,
214 virtual ir_rvalue *hir(exec_list *instructions,
272 virtual ir_rvalue *hir(exec_list *instructions,
298 virtual ir_rvalue *hir(exec_list *instructions,
370 virtual ir_rvalue *hir(exec_list *instructions,
491 virtual ir_rvalue *hir(exec_list *instructions,
519 virtual ir_rvalue *hir(exec_list *instructions,
550 virtual ir_rvalue *hir(exec_list *instructions,
607 virtual ir_rvalue *hir(exec_list *instructions,
630 virtual ir_rvalue *hir(exec_list *instructions,
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Dlower_if_to_cond_assign.cpp69 lower_if_to_cond_assign(exec_list *instructions, unsigned max_depth) in lower_if_to_cond_assign() argument
73 visit_list_elements(&v, instructions); in lower_if_to_cond_assign()
99 exec_list *instructions; in move_block_to_cond_assign() local
102 instructions = &if_ir->then_instructions; in move_block_to_cond_assign()
104 instructions = &if_ir->else_instructions; in move_block_to_cond_assign()
107 foreach_iter(exec_list_iterator, iter, *instructions) { in move_block_to_cond_assign()
/external/webkit/Source/JavaScriptCore/bytecompiler/
DBytecodeGenerator.cpp147 m_codeBlock->setInstructionCount(m_codeBlock->instructions().size()); in generate()
379 instructions().append(argumentsRegister->index()); in BytecodeGenerator()
387 instructions().append(argumentsRegister->index()); in BytecodeGenerator()
405 instructions().append(m_activationRegister->index()); in BytecodeGenerator()
421 instructions().append(m_activationRegister->index()); in BytecodeGenerator()
471 instructions().append(func->index()); in BytecodeGenerator()
476 instructions().append(m_thisRegister.index()); in BytecodeGenerator()
477 instructions().append(funcProto->index()); in BytecodeGenerator()
483 instructions().append(m_thisRegister.index()); in BytecodeGenerator()
539 instructions().append(reg->index()); in emitInitLazyRegister()
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/external/elfutils/tests/
Drun-show-ciefde.sh34 FDE[0]: instructions = 41 0e 08 85 02 42 0d 05 41 83 03 00
69 FDE[0]: instructions = 41 0e 08 85 02 42 0d 05 53 2e 08 50 2e 10 48 2e 00 58 2e 10 62 2e 00 63 2e 1…
73 FDE[1]: instructions = 41 0e 08 85 02 42 0d 05 4c 2e 10 00
77 FDE[2]: instructions = 41 0e 08 85 02 42 0d 05 41 83 03 00
81 FDE[3]: instructions = 41 0e 08 85 02 42 0d 05 41 83 03 00
85 FDE[4]: instructions = 41 0e 08 85 02 42 0d 05 41 86 03 41 83 04 53 2e 10 4e 2e 00 55 2e 10 00
89 FDE[5]: instructions = 41 0e 08 85 02 42 0d 05 41 86 03 41 83 04 5e 2e 10 00 00 00
93 FDE[6]: instructions = 41 0e 08 85 02 42 0d 05 41 83 03 00
97 FDE[7]: instructions = 41 0e 08 85 02 42 0d 05 41 83 03 00
101 FDE[8]: instructions = 41 0e 08 85 02 42 0d 05 41 83 03 5c 2e 10 00 00
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/external/oprofile/events/i386/atom/
Dunit_masks10 0x01 prefetcht0 Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed
11 0x06 sw_l2 Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed
12 0x08 prefetchnta Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed
49 0x02 cisc_decoded CISC macro instructions decoded
73 0x00 any Retired branch instructions
74 0x01 pred_not_taken Retired branch instructions that were predicted not-taken
75 0x02 mispred_not_taken Retired branch instructions that were mispredicted not-taken
76 0x04 pred_taken Retired branch instructions that were predicted taken
77 0x08 mispred_taken Retired branch instructions that were mispredicted taken
78 0x0A mispred Retired mispredicted branch instructions (precise event)
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/external/llvm/lib/Target/ARM/
DARM.td31 "Enable VFP2 instructions">;
33 "Enable VFP3 instructions",
36 "Enable NEON instructions",
39 "Enable Thumb2 instructions">;
47 "Enable divide instructions">;
49 "Enable Thumb2 extract and pack instructions">;
51 "Has data barrier (dmb / dsb) instructions">;
57 // Some processors have FP multiply-accumulate instructions that don't
58 // play nicely with other VFP / NEON instructions, and it's generally better
61 "Disable VFP / NEON MAC instructions">;
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/external/oprofile/events/mips/24K/
Devents21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether compl…
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions execut…
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions e…
32 event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed
33 event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (includ…
34 event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed
35 …ounters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0
37 event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions completed
38 event:0x14 counters:0 um:zero minimum:500 name:PREFETCH_INSNS : 20-0 PREFETCH instructions completed
44 event:0x1a counters:0 um:zero minimum:500 name:DSP_INSNS : 26-0 DSP instructions completed
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/external/oprofile/events/mips/34K/
Devents21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether compl…
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions execut…
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions e…
32 event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed
33 event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (includ…
34 event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed
35 …ounters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0
37 event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions completed
38 event:0x14 counters:0 um:zero minimum:500 name:PREFETCH_INSNS : 20-0 PREFETCH instructions completed
44 event:0x1a counters:0 um:zero minimum:500 name:DSP_INSNS : 26-0 DSP instructions completed
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/external/oprofile/events/mips/74K/
Devents20 …:500 name:PREDICTED_JR_31 : 2-0 JR $31 (return) instructions predicted including speculative instr…
21 …o register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determ…
24 …inimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache accesses including speculative instructions
35 …7-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions but operands no…
36 …8-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions due to operand(…
40 …ounters:0,2 um:zero minimum:500 name:JALR_JALR_HB_INSNS : 22-0 Graduated JALR/JALR.HB instructions
41 … name:DCACHE_LOAD_ACCESSES : 23-0 Counts all accesses to the data cache caused by load instructions
53 …:0,2 um:zero minimum:500 name:JR_NON_31_INSNS : 36-0 jr $xx (not $31) instructions graduated (at s…
54 event:0x25 counters:0,2 um:zero minimum:500 name:BRANCH_INSNS : 37-0 Branch instructions graduated,…
55 …BRANCH_LIKELY_INSNS : 38-0 Branch likely instructions graduated including CP1 and CP2 branch likel…
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/external/llvm/lib/Target/X86/
DX86.td31 "Enable conditional move instructions">;
38 "Enable MMX instructions">;
40 "Enable SSE instructions",
45 "Enable SSE2 instructions",
48 "Enable SSE3 instructions",
51 "Enable SSSE3 instructions",
54 "Enable SSE 4.1 instructions",
57 "Enable SSE 4.2 instructions",
60 "Enable 3DNow! instructions",
63 "Enable 3DNow! Athlon instructions",
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DX86InstrFormats.td136 // Attributes specific to X86 instructions...
237 // Templates for instructions that use a 16- or 32-bit segmented address as
255 // SI - SSE 1 & 2 scalar instructions
261 // AVX instructions have a 'v' prefix in the mnemonic
265 // SIi8 - SSE 1 & 2 scalar instructions
272 // AVX instructions have a 'v' prefix in the mnemonic
276 // PI - SSE 1 & 2 packed instructions
283 // AVX instructions have a 'v' prefix in the mnemonic
287 // PIi8 - SSE 1 & 2 packed instructions with immediate
294 // AVX instructions have a 'v' prefix in the mnemonic
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/external/chromium/chrome/browser/resources/
Dkeyboard_overlay.js279 var instructions = document.getElementById('instructions');
281 instructions.style.visibility = 'visible';
283 instructions.style.visibility = 'hidden';
398 var instructions = document.createElement('div');
399 instructions.id = 'instructions';
400 instructions.className = 'keyboard-overlay-instructions';
401 instructions.style.left = ((BASE_INSTRUCTIONS.left - BASE_KEYBOARD.left) *
403 instructions.style.top = ((BASE_INSTRUCTIONS.top - BASE_KEYBOARD.top) *
405 instructions.style.width = (width * BASE_INSTRUCTIONS.width /
407 instructions.style.height = (height * BASE_INSTRUCTIONS.height /
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/external/oprofile/events/ppc64/power5+/
Devents25 …:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP1 : (Group 1 pm_utilization) Run instructions completed
33 …m:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP2 : (Group 2 pm_completion) Run instructions completed
41 …ro minimum:1000 name:PM_RUN_INST_CMPL_GRP3 : (Group 3 pm_group_dispatch) Run instructions completed
45 …0 um:zero minimum:1000 name:PM_0INST_CLB_CYC_GRP4 : (Group 4 pm_clb1) Cycles no instructions in CLB
46 …:1 um:zero minimum:1000 name:PM_2INST_CLB_CYC_GRP4 : (Group 4 pm_clb1) Cycles 2 instructions in CLB
49 …rs:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP4 : (Group 4 pm_clb1) Run instructions completed
53 …:0 um:zero minimum:1000 name:PM_5INST_CLB_CYC_GRP5 : (Group 5 pm_clb2) Cycles 5 instructions in CLB
54 …:1 um:zero minimum:1000 name:PM_6INST_CLB_CYC_GRP5 : (Group 5 pm_clb2) Cycles 6 instructions in CLB
56 …nters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP5 : (Group 5 pm_clb2) IOPS instructions completed
57 …rs:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP5 : (Group 5 pm_clb2) Run instructions completed
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/external/oprofile/events/mips/1004K/
Devents21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether compl…
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions execut…
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions e…
32 event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed
33 event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (includ…
34 event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed
35 …ounters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0
37 event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions completed
38 event:0x14 counters:0 um:zero minimum:500 name:PREFETCH_INSNS : 20-0 PREFETCH instructions completed
44 event:0x1a counters:0 um:zero minimum:500 name:DSP_INSNS : 26-0 DSP instructions completed
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/external/llvm/docs/HistoricalNotes/
D2002-05-12-InstListChange.txt12 instructions. To iterate over instructions, we must actually iterate over
13 the instlist, and access the instructions through the instlist.
22 instructions.
24 Additionally, adding or removing instructions to a basic block
29 the instructions be represented with a doubly linked list in the
30 instructions themselves, instead of an external data structure. This is
40 Iteration over the instructions in a basic block remains the simple:
46 After converting instructions over, I'll convert basic blocks and
/external/llvm/lib/Target/Mips/
DMips.td44 "true", "Enable vector FPU instructions.">;
46 "Enable 'signext in register' instructions.">;
48 "Enable 'conditional move' instructions.">;
50 "Enable 'multiply add/sub' instructions.">;
52 "Enable 'min/max' instructions.">;
54 "Enable 'byte/half swap' instructions.">;
56 "Enable 'count leading bits' instructions.">;
86 // Mips32/Mips32r2 instructions and a custom vector fpu processor.
/external/proguard/src/proguard/classfile/editor/
DCodeAttributeEditor.java151 public void insertBeforeInstruction(int instructionOffset, Instruction[] instructions) in insertBeforeInstruction() argument
159 preInsertions[instructionOffset] = new CompositeInstruction(instructions); in insertBeforeInstruction()
193 public void replaceInstruction(int instructionOffset, Instruction[] instructions) in replaceInstruction() argument
201 replacements[instructionOffset] = new CompositeInstruction(instructions); in replaceInstruction()
234 public void insertAfterInstruction(int instructionOffset, Instruction[] instructions) in insertAfterInstruction() argument
242 postInsertions[instructionOffset] = new CompositeInstruction(instructions); in insertAfterInstruction()
1071 private Instruction[] instructions; field in CodeAttributeEditor.CompositeInstruction
1074 private CompositeInstruction(Instruction[] instructions) in CompositeInstruction() argument
1076 this.instructions = instructions; in CompositeInstruction()
1084 for (int index = 0; index < instructions.length; index++) in shrink()
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/external/oprofile/events/arm/armv7-ca9/
Devents12 …name:IC_DEP_STALL : Number of cycles where CPU is ready to accept new instructions but does not re…
13 …o minimum:500 name:DC_DEP_STALL : Number of cycles where CPU has some instructions that it cannot …
14 event:0x63 counters:1,2,3,4,5,6 um:zero minimum:500 name:STREX_PASS : Number of STREX instructions …
15 event:0x64 counters:1,2,3,4,5,6 um:zero minimum:500 name:STREX_FAILS : Number of STREX instructions…
19 event:0x68 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_RENAME : Number of instructions going …
23 event:0x70 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_MAIN_EXEC : Number of instructions bei…
24 event:0x71 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_SND_EXEC : Number of instructions bein…
25 event:0x72 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_LSU : Number of instructions being exe…
26 …3,4,5,6 um:zero minimum:500 name:INS_FP_RR : Number of floating-point instructions going through t…
27 event:0x74 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_NEON_RR : Number of NEON instructions …
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/external/oprofile/events/mips/25K/
Devents7 event:0x1 counters:0,1 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions
8 event:0x2 counters:0,1 um:zero minimum:500 name:FP_INSNS_ISSUED : FPU instructions issued
9 event:0x3 counters:0,1 um:zero minimum:500 name:INT_INSNS_ISSUED : Integer instructions issued
10 event:0x4 counters:0,1 um:zero minimum:500 name:LOAD_INSNS_ISSUED : Load instructions issued
11 event:0x5 counters:0,1 um:zero minimum:500 name:STORE_INSNS_ISSUED : Store instructions issued
12 event:0x6 counters:0,1 um:zero minimum:500 name:BRANCHES_JUMPS_ISSUED : Branch/Jump instructions is…
20 …SN_FP_DATAPATH_COMPLETED : Instructions completed in FPU datapath (computational instructions only)
29 event:0xf counters:0,1 um:zero minimum:500 name:JR_RPD_MISSPREDICTED : JR instructions that mispred…
50 … um:zero minimum:500 name:INSNS_FETCHED_FROM_ICACHE : Total number of instructions fetched from th…
81 event:0x27 counters:0,1 um:zero minimum:500 name:LOAD_STORE_ISSUED : Load/store instructions issued
/external/oprofile/events/i386/core/
Devents6 event:0xc0 counters:0,1 um:zero minimum:6000 name:INST_RETIRED : number of instructions retired
45 event:0x4b counters:0,1 um:sse_miss minimum:500 name:SSE_PREF_MISS : SSE instructions that missed a…
74 event:0x88 counters:0,1 um:zero minimum:3000 name:BR_INST_EXEC : Branch instructions executed (not …
75 event:0x89 counters:0,1 um:zero minimum:3000 name:BR_MISSP_EXEC : Branch instructions executed that…
76 event:0x8a counters:0,1 um:zero minimum:3000 name:BR_BAC_MISSP_EXEC : Branch instructions executed …
77 event:0x8b counters:0,1 um:zero minimum:3000 name:BR_CND_EXEC : Conditional Branch instructions exe…
78 …:0,1 um:zero minimum:3000 name:BR_CND_MISSP_EXEC : Conditional Branch instructions executed that w…
79 event:0x8d counters:0,1 um:zero minimum:3000 name:BR_IND_EXEC : Indirect Branch instructions execut…
80 event:0x8e counters:0,1 um:zero minimum:3000 name:BR_IND_MISSP_EXEC : Indirect Branch instructions …
81 event:0x8f counters:0,1 um:zero minimum:3000 name:BR_RET_EXEC : Return Branch instructions executed
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