Searched refs:irq_state (Results 1 – 4 of 4) sorted by relevance
172 if (s->gic.irq_state[irq].pending) { in nvic_readl()178 if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending) in nvic_readl()181 if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending) in nvic_readl()184 if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending) in nvic_readl()207 if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0); in nvic_readl()208 if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1); in nvic_readl()209 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3); in nvic_readl()210 if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7); in nvic_readl()211 if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8); in nvic_readl()212 if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10); in nvic_readl()[all …]
52 #define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 153 #define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 054 #define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled55 #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)56 #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)57 #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)58 #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)59 #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)60 #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)61 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1[all …]
134 qemu_put_be32(f, s->irq_state[i]); in pci_device_save()150 s->irq_state[i] = qemu_get_be32(f); in pci_device_load()258 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); in do_pci_register_device()653 change = level - pci_dev->irq_state[irq_num]; in pci_set_irq()657 pci_dev->irq_state[irq_num] = level; in pci_set_irq()
160 int irq_state[4]; member