Searched refs:is64BitVector (Results 1 – 3 of 3) sorted by relevance
262 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);1437 bool is64BitVector) { in GetVLDSTAlign() argument1439 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()1468 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local1469 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector); in SelectVLD()1495 if (!is64BitVector) in SelectVLD()1511 if (is64BitVector || NumVecs <= 2) { in SelectVLD()1512 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()1569 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()1596 bool is64BitVector = VT.is64BitVector(); in SelectVST() local[all …]
3780 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()3808 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()3831 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()3857 if (VT.is64BitVector() && EltSz == 32) in isVZIP_v_undef_Mask()4140 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()4623 assert(Op0.getValueType().is64BitVector() && in LowerMUL()4624 Op1.getValueType().is64BitVector() && in LowerMUL()5728 if (VT.is64BitVector() || VT.is128BitVector()) in PerformMULCombine()6388 if (!VT.is64BitVector()) in CombineVLDDUP()
469 bool is64BitVector() const { in is64BitVector() function