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Searched refs:r32 (Results 1 – 25 of 27) sorted by relevance

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/external/valgrind/main/none/tests/x86/
Dinsn_cmov.def193 cmova eflags[0x041,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
194 cmova eflags[0x041,0x001] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
195 cmova eflags[0x041,0x040] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
196 cmova eflags[0x041,0x041] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
197 cmova eflags[0x041,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
198 cmova eflags[0x041,0x001] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
199 cmova eflags[0x041,0x040] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
200 cmova eflags[0x041,0x041] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
201 cmovae eflags[0x001,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
202 cmovae eflags[0x001,0x001] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
[all …]
Dinsn_basic.def47 adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333]
48 adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334]
55 adcl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
56 adcl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
57 adcl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
58 adcl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000]
59 adcl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
60 adcl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
74 addl imm8[12] r32.ud[87654321] => 1.ud[87654333]
78 addl r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
[all …]
Dinsn_mmxext.def6 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[1234]
7 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[5678]
8 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[4321]
9 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[8765]
10 pinsrw imm8[0] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765]
11 pinsrw imm8[1] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765]
12 pinsrw imm8[2] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,65535,8765]
13 pinsrw imm8[3] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,4321,65535]
22 pmovmskb mm.uq[0x8000000080008088] r32.ud[0] => 1.ud[0x8b]
Dinsn_sse.def51 cvtsi2ss r32.sd[12] xmm.ps[1.11,2.22,3.33,4.44] => 1.ps[12.0,2.22,3.33,4.44]
53 cvtss2si xmm.ps[12.34,56.78,43.21,87.65] r32.sd[99] => 1.sd[12]
54 cvtss2si m128.ps[56.78,12.34,87.65,43.21] r32.sd[99] => 1.sd[57]
57 cvttss2si xmm.ps[12.34,56.78,43.21,87.65] r32.sd[99] => 1.sd[12]
58 cvttss2si m128.ps[56.78,12.34,87.65,43.21] r32.sd[99] => 1.sd[56]
79 movmskps xmm.ps[12.34,-56.78,43.21,-87.65] r32.sd[0] => 1.sd[10]
97 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[1234]
98 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[5678]
99 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[4321]
100 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[8765]
[all …]
Dinsn_sse2.def63 cvtsd2si xmm.pd[12.34,56.78] r32.sd[99] => 1.sd[12]
64 cvtsd2si m128.pd[56.78,12.34] r32.sd[99] => 1.sd[57]
67 cvtsi2sd r32.sd[12] xmm.pd[1.11,2.22] => 1.pd[12.0,2.22]
77 cvttsd2si xmm.pd[12.34,56.78] r32.sd[99] => 1.sd[12]
78 cvttsd2si m128.pd[56.78,12.34] r32.sd[99] => 1.sd[56]
95 movd r32.sd[1234] xmm.sd[1111,2222,3333,4444] => 1.sd[1234,0,0,0]
97 movd xmm.sd[1234,2222,3333,4444] r32.sd[1111] => 1.sd[1234]
110 movmskpd xmm.pd[1234.5678,-1234.5678] r32.sd[0] => 1.sd[2]
112 movnti r32.sd[12345678] m32.sd[11111111] => 1.sd[12345678]
173 pextrw imm8[0] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1234]
[all …]
Dgen_insn_test.pl10 r32 => "reg32_t",
71 { r8 => "al", r16 => "ax", r32 => "eax" },
72 { r8 => "bl", r16 => "bx", r32 => "ebx" },
73 { r8 => "cl", r16 => "cx", r32 => "ecx" },
74 { r8 => "dl", r16 => "dx", r32 => "edx" },
Dinsn_mmx.def1 movd r32.sd[1234] mm.sd[1111,2222] => 1.sd[1234,0]
3 movd mm.sd[1234,2222] r32.sd[1111] => 1.sd[1234]
/external/valgrind/main/none/tests/amd64/
Dinsn_basic.def27 adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333]
28 adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334]
35 adcl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
36 adcl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
37 adcl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
38 adcl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000]
39 adcl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
40 adcl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
68 addl imm8[12] r32.ud[87654321] => 1.ud[87654333]
72 addl r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
[all …]
Dinsn_sse.def51 cvtsi2ss r32.sd[12] xmm.ps[1.11,2.22,3.33,4.44] => 1.ps[12.0,2.22,3.33,4.44]
53 cvtss2si xmm.ps[12.34,56.78,43.21,87.65] r32.sd[99] => 1.sd[12]
54 cvtss2si m128.ps[56.78,12.34,87.65,43.21] r32.sd[99] => 1.sd[57]
57 cvttss2si xmm.ps[12.34,56.78,43.21,87.65] r32.sd[99] => 1.sd[12]
58 cvttss2si m128.ps[56.78,12.34,87.65,43.21] r32.sd[99] => 1.sd[56]
79 movmskps xmm.ps[12.34,-56.78,43.21,-87.65] r32.sd[0] => 1.sd[10]
97 pextrw imm8[0] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[1234]
98 pextrw imm8[1] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[5678]
99 pextrw imm8[2] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[4321]
100 pextrw imm8[3] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[8765]
[all …]
Dinsn_sse2.def63 cvtsd2si xmm.pd[12.34,56.78] r32.sd[99] => 1.sd[12]
64 cvtsd2si m128.pd[56.78,12.34] r32.sd[99] => 1.sd[57]
67 cvtsi2sd r32.sd[12] xmm.pd[1.11,2.22] => 1.pd[12.0,2.22]
77 cvttsd2si xmm.pd[12.34,56.78] r32.sd[99] => 1.sd[12]
78 cvttsd2si m128.pd[56.78,12.34] r32.sd[99] => 1.sd[56]
95 movd r32.sd[1234] xmm.sd[1111,2222,3333,4444] => 1.sd[1234,0,0,0]
97 movd xmm.sd[1234,2222,3333,4444] r32.sd[1111] => 1.sd[1234]
110 movmskpd xmm.pd[1234.5678,-1234.5678] r32.sd[0] => 1.sd[2]
112 movnti r32.sd[12345678] m32.sd[11111111] => 1.sd[12345678]
173 pextrw imm8[0] xmm.uw[1234,5678,4321,8765,1111,2222,3333,4444] r32.ud[0xffffffff] => 2.ud[1234]
[all …]
Dgen_insn_test.pl10 r32 => "reg32_t",
87 { r8 => "r9b", r16 => "r9w", r32 => "r9d", r64 => "r9" },
88 { r8 => "r10b", r16 => "r10w", r32 => "r10d", r64 => "r10" },
89 { r8 => "r11b", r16 => "r11w", r32 => "r11d", r64 => "r11" },
90 { r8 => "r12b", r16 => "r12w", r32 => "r12d", r64 => "r12" },
91 { r8 => "al", r16 => "ax", r32 => "eax", r64 => "rax" },
92 { r8 => "bl", r16 => "bx", r32 => "ebx", r64 => "rbx" },
93 { r8 => "cl", r16 => "cx", r32 => "ecx", r64 => "rcx" },
94 { r8 => "dl", r16 => "dx", r32 => "edx", r64 => "rdx" },
Dinsn_mmx.def9 movd r32.sd[1234] mm.sd[1111,2222] => 1.sd[1234,0]
10 movd mm.sd[1234,2222] r32.sd[1111] => 1.sd[1234]
/external/openssl/crypto/
Dia64cpuid.S22 { .mii; ld4 r2=[r32]
30 cmpxchg4.acq r2=[r32],r8,ar.ccv
135 addp4 r32=0,r32
138 { .mib; and r2=7,r32
143 { .mib; st1 [r32]=r0,1
152 { .mmi; st1 [r32]=r0,1;;
153 and r2=7,r32 }
158 { .mmi; st8 [r32]=r0,8
/external/openssl/crypto/bn/asm/
Dia64.S185 { .mib; ADDP r14=0,r32 // rp
196 { .mii; (p16) ld8 r32=[r16],8 // b=*(bp++)
238 { .mib; ADDP r14=0,r32 // rp
249 { .mii; (p16) ld8 r32=[r16],8 // b=*(bp++)
311 { .mmi; ADDP r14=0,r32 // rp
335 { .mii; (p25) getf.sig r32=f44 // high
372 { .mfb; (p20) stf8 [r32]=f37,8
415 { .mmi; ADDP r14=0,r32 // rp
418 { .mii; ADDP r16=0,r32 // rp copy
440 { .mmi; (p24) getf.sig r32=f40 // high
[all …]
/external/kernel-headers/original/asm-x86/
Dacpi_32.h71 #define ACPI_DIV_64_BY_32(n_hi, n_lo, d32, q32, r32) \ argument
73 :"=a"(q32), "=d"(r32) \
/external/llvm/lib/Target/CellSPU/
DSPUInstrInfo.td69 def r32: LoadDForm<R32C>;
101 def r32: LoadAForm<R32C>;
133 def r32: LoadXForm<R32C>;
181 def r32: StoreDForm<R32C>;
211 def r32: StoreAForm<R32C>;
243 def r32: StoreXForm<R32C>;
356 def r32: ILRegInst<R32C, s16imm_i32, immSExt16>;
381 def r32: ILHURegInst<R32C, u16imm_i32, hi16>;
413 def r32: ILARegInst<R32C, u18imm, imm18>;
450 def r32: IOHLRegInst<R32C, i32imm>;
[all …]
DSPU64InstrInfo.td22 // [Note: this may be moot, since gb produces v4i32 or r32.]
/external/libffi/src/sh64/
Dsysv.S61 st.q r15, 40, r32
75 add r8, r63, r32
247 ptabs/l r32, tr0
304 ld.q r15, 40, r32
/external/chromium/base/win/
Dscoped_variant.cc168 void ScopedVariant::Set(float r32) { in Set() argument
171 var_.fltVal = r32; in Set()
Dscoped_variant.h102 void Set(float r32);
/external/valgrind/main/VEX/priv/
Dhost_x86_isel.c1653 HReg r32 = lookupIRTemp(env, e->Iex.RdTmp.tmp); in iselCondCode_wrk() local
1655 addInstr(env, X86Instr_Test32(1,X86RM_Reg(r32))); in iselCondCode_wrk()
3221 HReg r32 = newVRegI(env); in iselVecExpr_wrk() local
3226 addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Mem(am), r32)); in iselVecExpr_wrk()
3227 addInstr(env, X86Instr_Unary32(Xun_NEG, r32)); in iselVecExpr_wrk()
3228 addInstr(env, X86Instr_Alu32R(Xalu_SBB, X86RMI_Reg(r32), r32)); in iselVecExpr_wrk()
3229 addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(r32), am)); in iselVecExpr_wrk()
/external/qemu-pc-bios/bochs/bios/
Drombios.c799 } r32;
4531 if(regs.u.r32.edx == 0x534D4150)
4564 regs.u.r32.ebx = 1;
4569 regs.u.r32.ebx = 2;
4574 regs.u.r32.ebx = 3;
4581 regs.u.r32.ebx = 4;
4586 regs.u.r32.ebx = 5;
4593 regs.u.r32.ebx = 5;
4600 regs.u.r32.ebx = 6;
4602 regs.u.r32.ebx = 0;
[all …]
/external/llvm/lib/Target/PTX/
DPTXRegisterInfo.td319 def R32 : PTXReg<"r32">;
/external/webkit/Tools/iExploder/iexploder-1.7.2/
DChangeLog.txt767 r32 | thomas | 2006-04-19 16:22:33 +0200 (Wed, 19 Apr 2006) | 1 line
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td251 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
282 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX

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