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Searched refs:v8f32 (Results 1 – 10 of 10) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DValueTypes.h73 v8f32 = 30, // 8 x f32 enumerator
208 case v8f32: return f32; in getVectorElementType()
225 case v8f32: return 8; in getVectorNumElements()
282 case v8f32: in getSizeInBits()
365 if (NumElements == 8) return MVT::v8f32; in getVectorVT()
489 return (V == MVT::v8f32 || V == MVT::v4f64 || V == MVT::v32i8 || in is256BitVector()
DValueTypes.td54 def v8f32 : ValueType<256, 30>; // 8 x f32 vector value
/external/llvm/lib/VMCore/
DValueTypes.cpp132 case MVT::v8f32: return "v8f32"; in getEVTString()
179 case MVT::v8f32: return VectorType::get(Type::getFloatTy(Context), 8); in getTypeForEVT()
/external/llvm/lib/Target/X86/
DX86CallingConv.td46 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
162 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
178 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
277 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
285 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
DX86InstrFragmentsSIMD.td191 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
224 (v8f32 (alignedload node:$ptr))>;
256 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
DX86InstrSSE.td182 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
290 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
296 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
1283 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1337 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1343 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1542 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
1605 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1763 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
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DX86RegisterInfo.td458 def VR256 : RegisterClass<"X86", [v32i8, v8i32, v4i64, v8f32, v4f64], 256,
DX86ISelLowering.cpp984 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); in X86TargetLowering()
990 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); in X86TargetLowering()
994 setOperationAction(ISD::FADD, MVT::v8f32, Legal); in X86TargetLowering()
995 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); in X86TargetLowering()
996 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); in X86TargetLowering()
997 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); in X86TargetLowering()
998 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); in X86TargetLowering()
999 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); in X86TargetLowering()
1293 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: in findRepresentativeClass()
3835 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); in getZeroVector()
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/external/llvm/utils/TableGen/
DCodeGenTarget.cpp87 case MVT::v8f32: return "MVT::v8f32"; in getEnumName()
/external/llvm/include/llvm/
DIntrinsics.td136 def llvm_v8f32_ty : LLVMType<v8f32>; // 8 x float