Searched refs:vvvv (Results 1 – 5 of 5) sorted by relevance
1266 insn->vvvv = (Reg)fixupRegValue(insn, in fixupReg()1268 insn->vvvv, in fixupReg()1448 insn->vvvv = vvvvFromVEX3of3(insn->vexPrefix[2]); in readVVVV()1450 insn->vvvv = vvvvFromVEX2of2(insn->vexPrefix[1]); in readVVVV()
490 Reg vvvv; member
507 translateRegister(mcInst, insn.vvvv); in translateOperand()
326 was more like 100:1. You can use the -vvvv option to mon-
329 was more like 100:1. You can use the −vvvv option to mon