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/external/llvm/test/Transforms/InstCombine/
Dudivrem-change-width.ll7 %conv = zext i8 %a to i32
8 %conv2 = zext i8 %b to i32
17 %conv = zext i8 %a to i32
18 %conv2 = zext i8 %b to i32
27 %conv = zext i8 %a to i32
28 %conv2 = zext i8 %b to i32
33 ; CHECK: zext
37 %conv = zext i8 %a to i32
38 %conv2 = zext i8 %b to i32
43 ; CHECK: zext
[all …]
Dcast.ll15 %c1 = zext i8 %A to i16 ; <i16> [#uses=1]
16 %c2 = zext i16 %c1 to i32 ; <i32> [#uses=1]
17 %Ret = zext i32 %c2 to i64 ; <i64> [#uses=1]
19 ; CHECK: %Ret = zext i8 %A to i64
26 %c2 = zext i8 %c1 to i64 ; <i64> [#uses=1]
35 %c = zext i1 %COND to i8 ; <i8> [#uses=1]
37 %result = zext i8 %c to i32 ; <i32> [#uses=1]
40 ; CHECK: %result = zext i1 %COND to i32
46 %c = zext i1 %B to i8 ; <i8> [#uses=1]
48 %result = zext i8 %c to i32 ; <i32> [#uses=1]
[all …]
Dtrunc.ll11 %d = zext i32 %c to i64
33 %d = zext i32 %c to i64
44 %d = zext i32 %x to i64
54 %B = zext i32 %A to i128
64 %B = zext i64 %A to i128
75 %B = zext i64 %A to i128
80 ; CHECK: %B = zext i64 %A to i92
86 %tmp38 = zext i32 %A to i128
87 %tmp32 = zext i32 %B to i128
93 ; CHECK: %tmp38 = zext i32 %A to i64
[all …]
Dzext-bool-add-sub.ll1 ; RUN: opt < %s -instcombine -S | not grep zext
5 %y = zext i1 %x to i32
12 %y = zext i1 %x to i32
19 %y = zext i1 %x to i32
26 %y = zext i1 %x to i32
/external/llvm/test/CodeGen/X86/
D2008-12-02-IllegalResultType.ll12 %2 = zext i8 %1 to i64 ; <i64> [#uses=1]
14 %4 = zext i1 %3 to i64 ; <i64> [#uses=1]
17 %7 = zext i1 %6 to i8 ; <i8> [#uses=1]
19 %9 = zext i8 %8 to i64 ; <i64> [#uses=1]
21 %11 = zext i1 %10 to i8 ; <i8> [#uses=1]
23 %13 = zext i8 %12 to i64 ; <i64> [#uses=1]
25 %15 = zext i1 %14 to i8 ; <i8> [#uses=1]
27 %17 = zext i8 %16 to i64 ; <i64> [#uses=1]
29 %19 = zext i1 %18 to i8 ; <i8> [#uses=1]
31 %21 = zext i8 %20 to i64 ; <i64> [#uses=1]
[all …]
Dvec_zext.ll6 %G = zext <4 x i16> %F to <4 x i32>
8 %Y = zext <4 x i16> %H to <4 x i32>
16 %G = zext <4 x i16> %F to <4 x i64>
18 %Y = zext <4 x i16> %H to <4 x i64>
26 %G = zext <4 x i32> %F to <4 x i64>
28 %Y = zext <4 x i32> %H to <4 x i64>
35 %G = zext <4 x i8> %F to <4 x i16>
37 %Y = zext <4 x i8> %H to <4 x i16>
44 %G = zext <4 x i8> %F to <4 x i32>
46 %Y = zext <4 x i8> %H to <4 x i32>
[all …]
Dchange-compare-stride-1.ll19 %0 = zext i16 %i.0.reg2mem.0.ph to i32 ; <i32> [#uses=1]
32 %2 = zext i16 %j.0.reg2mem.0 to i32 ; <i32> [#uses=1]
35 %5 = zext i32 %4 to i64 ; <i64> [#uses=1]
39 %9 = zext i32 %8 to i64 ; <i64> [#uses=1]
43 %13 = zext i32 %12 to i64 ; <i64> [#uses=1]
47 %17 = zext i32 %16 to i64 ; <i64> [#uses=1]
50 %20 = zext i32 %3 to i64 ; <i64> [#uses=1]
54 %24 = zext i32 %23 to i64 ; <i64> [#uses=1]
58 %28 = zext i32 %27 to i64 ; <i64> [#uses=1]
62 %32 = zext i32 %31 to i64 ; <i64> [#uses=1]
[all …]
Dshift-double.ll5 %shift.upgrd.1 = zext i8 %C to i64 ; <i64> [#uses=1]
11 %shift.upgrd.2 = zext i8 %C to i64 ; <i64> [#uses=1]
17 %shift.upgrd.3 = zext i8 %C to i64 ; <i64> [#uses=1]
23 %shift.upgrd.4 = zext i8 %C to i32 ; <i32> [#uses=1]
26 %shift.upgrd.5 = zext i8 %Cv to i32 ; <i32> [#uses=1]
33 %shift.upgrd.6 = zext i8 %C to i16 ; <i16> [#uses=1]
36 %shift.upgrd.7 = zext i8 %Cv to i16 ; <i16> [#uses=1]
D2008-09-11-CoalescerBug.ll10 %2 = zext i16 %1 to i32 ; <i32> [#uses=1]
14 %6 = zext i1 %5 to i32 ; <i32> [#uses=1]
16 %8 = zext i1 %7 to i32 ; <i32> [#uses=1]
19 %11 = zext i1 %10 to i32 ; <i32> [#uses=1]
22 %14 = zext i1 %13 to i32 ; <i32> [#uses=1]
25 %17 = zext i1 %16 to i32 ; <i32> [#uses=1]
Dconditional-indecrement.ll5 %inc = zext i1 %not.cmp to i32
16 %inc = zext i1 %cmp to i32
27 %inc = zext i1 %cmp to i32
38 %inc = zext i1 %not.cmp to i32
49 %inc = zext i1 %not.cmp to i32
60 %inc = zext i1 %cmp to i32
71 %inc = zext i1 %cmp to i32
82 %inc = zext i1 %not.cmp to i32
D2009-06-02-RewriterBug.ll15 %conv = zext i32 undef to i64 ; <i64> [#uses=1]
16 %conv11 = zext i32 undef to i64 ; <i64> [#uses=1]
18 %conv19 = zext i32 %tmp18 to i64 ; <i64> [#uses=1]
20 %conv31 = zext i32 %tmp30 to i64 ; <i64> [#uses=4]
22 %conv442709 = zext i8 %ptrincdec3065 to i64 ; <i64> [#uses=1]
24 %conv632707 = zext i8 undef to i64 ; <i64> [#uses=1]
41 %conv2852690 = zext i8 undef to i64 ; <i64> [#uses=1]
69 %conv4932682 = zext i8 undef to i64 ; <i64> [#uses=1]
72 %conv5032681 = zext i8 %ptrincdec4903012 to i64 ; <i64> [#uses=1]
75 %conv5132680 = zext i8 %ptrincdec5003009 to i64 ; <i64> [#uses=1]
[all …]
/external/llvm/lib/Target/CellSPU/
DSPU128InstrInfo.td7 // zext 32->128: Zero extend 32-bit to 128-bit
8 def : Pat<(i128 (zext R32C:$rSrc)),
11 // zext 64->128: Zero extend 64-bit to 128-bit
12 def : Pat<(i128 (zext R64C:$rSrc)),
15 // zext 16->128: Zero extend 16-bit to 128-bit
16 def : Pat<(i128 (zext R16C:$rSrc)),
19 // zext 8->128: Zero extend 8-bit to 128-bit
20 def : Pat<(i128 (zext R8C:$rSrc)),
/external/llvm/test/CodeGen/MSP430/
Dbit.ll11 %t3 = zext i1 %t2 to i8
20 %t3 = zext i1 %t2 to i8
29 %t3 = zext i1 %t2 to i8
39 %t4 = zext i1 %t3 to i8
49 %t4 = zext i1 %t3 to i8
59 %t4 = zext i1 %t3 to i8
69 %t4 = zext i1 %t3 to i8
80 %t5 = zext i1 %t4 to i8
92 %t3 = zext i1 %t2 to i16
101 %t3 = zext i1 %t2 to i16
[all …]
Dsetcc.ll8 %t3 = zext i1 %t2 to i16
20 %t3 = zext i1 %t2 to i16
30 %t2 = zext i1 %t1 to i16
42 %t2 = zext i1 %t1 to i16
53 %t2 = zext i1 %t1 to i16
64 %t2 = zext i1 %t1 to i16
74 %t2 = zext i1 %t1 to i16
85 %t2 = zext i1 %t1 to i16
95 %t2 = zext i1 %t1 to i16
101 %t2 = zext i1 %t1 to i16
[all …]
/external/llvm/test/ExecutionEngine/
Dtest-cast.ll9 zext i1 true to i8 ; <i8>:2 [#uses=0]
10 zext i1 true to i8 ; <i8>:3 [#uses=0]
11 zext i1 true to i16 ; <i16>:4 [#uses=0]
12 zext i1 true to i16 ; <i16>:5 [#uses=0]
13 zext i1 true to i32 ; <i32>:6 [#uses=0]
14 zext i1 true to i32 ; <i32>:7 [#uses=0]
15 zext i1 true to i64 ; <i64>:8 [#uses=0]
16 zext i1 true to i64 ; <i64>:9 [#uses=0]
33 zext i8 4 to i16 ; <i16>:26 [#uses=0]
34 zext i8 4 to i16 ; <i16>:27 [#uses=0]
[all …]
Dtest-shift.ll5 %shift.upgrd.1 = zext i8 %shamt to i32 ; <i32> [#uses=1]
8 %shift.upgrd.2 = zext i8 %shamt to i32 ; <i32> [#uses=1]
13 %shift.upgrd.5 = zext i8 %shamt to i32 ; <i32> [#uses=1]
16 %shift.upgrd.6 = zext i8 %shamt to i32 ; <i32> [#uses=1]
20 %shift.upgrd.7 = zext i8 %shamt to i64 ; <i64> [#uses=1]
23 %shift.upgrd.8 = zext i8 %shamt to i64 ; <i64> [#uses=1]
26 %shift.upgrd.9 = zext i8 %shamt to i64 ; <i64> [#uses=1]
29 %shift.upgrd.10 = zext i8 %shamt to i64 ; <i64> [#uses=1]
/external/llvm/test/CodeGen/PTX/
Dsetp.ll8 %z = zext i1 %p to i32
17 %z = zext i1 %p to i32
26 %z = zext i1 %p to i32
35 %z = zext i1 %p to i32
44 %z = zext i1 %p to i32
53 %z = zext i1 %p to i32
62 %z = zext i1 %p to i32
71 %z = zext i1 %p to i32
80 %z = zext i1 %p to i32
89 %z = zext i1 %p to i32
[all …]
/external/llvm/test/Analysis/ScalarEvolution/
Dfold.ll4 %A = zext i8 %x to i12
6 ; CHECK: zext i8 %x to i16
11 %A = zext i8 %x to i16
19 %A = zext i8 %x to i16
47 ; CHECK-NEXT: (zext i32 ([[EXPR]]) to i34)
48 %F = zext i16 %B to i30
51 %G = zext i16 %B to i32
54 %H = zext i16 %B to i34
56 ; CHECK-NEXT: (zext i32 ([[EXPR]]) to i34)
/external/llvm/test/Transforms/IndVarSimplify/
D2009-04-15-shorten-iv-vars-2.ll36 %4 = zext i32 %3 to i64 ; <i64> [#uses=1]
41 %9 = zext i32 %8 to i64 ; <i64> [#uses=1]
45 %13 = zext i32 %1 to i64 ; <i64> [#uses=1]
54 %21 = zext i32 %20 to i64 ; <i64> [#uses=1]
60 %27 = zext i32 %26 to i64 ; <i64> [#uses=1]
64 %31 = zext i32 %17 to i64 ; <i64> [#uses=1]
73 %39 = zext i32 %38 to i64 ; <i64> [#uses=1]
79 %45 = zext i32 %44 to i64 ; <i64> [#uses=1]
83 %49 = zext i32 %35 to i64 ; <i64> [#uses=1]
90 %55 = zext i32 %54 to i64 ; <i64> [#uses=1]
[all …]
/external/llvm/test/CodeGen/Generic/
Di128-addsub.ll5 %tmp1 = zext i64 %AL to i128 ; <i128> [#uses=1]
6 %tmp23 = zext i64 %AH to i128 ; <i128> [#uses=1]
9 %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
10 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
24 %tmp1 = zext i64 %AL to i128 ; <i128> [#uses=1]
25 %tmp23 = zext i64 %AH to i128 ; <i128> [#uses=1]
28 %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
29 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
/external/llvm/test/CodeGen/Blackfin/
Daddsub-i128.ll8 %tmp1 = zext i64 %AL to i128 ; <i128> [#uses=1]
9 %tmp23 = zext i64 %AH to i128 ; <i128> [#uses=1]
12 %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
13 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
27 %tmp1 = zext i64 %AL to i128 ; <i128> [#uses=1]
28 %tmp23 = zext i64 %AH to i128 ; <i128> [#uses=1]
31 %tmp67 = zext i64 %BL to i128 ; <i128> [#uses=1]
32 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
/external/llvm/test/CodeGen/XCore/
Dmisc-intrinsics.ll7 declare i32 @llvm.xcore.zext(i32, i32)
31 define i32 @zext(i32 %a, i32 %b) {
32 ; CHECK: zext:
33 ; CHECK: zext r0, r1
34 %result = call i32 @llvm.xcore.zext(i32 %a, i32 %b)
40 ; CHECK: zext r0, 4
41 %result = call i32 @llvm.xcore.zext(i32 %a, i32 4)
Dladd_lsub_combine.ll6 %0 = zext i32 %x to i64 ; <i64> [#uses=1]
7 %1 = zext i32 %y to i64 ; <i64> [#uses=1]
19 %0 = zext i32 %x to i64 ; <i64> [#uses=1]
20 %1 = zext i32 %y to i64 ; <i64> [#uses=1]
33 %0 = zext i32 %y to i64 ; <i64> [#uses=1]
46 %0 = zext i32 %x to i64 ; <i64> [#uses=1]
59 %0 = zext i32 %y to i64 ; <i64> [#uses=1]
Daddsub64.ll24 %0 = zext i32 %b to i64
25 %1 = zext i32 %c to i64
48 %0 = zext i32 %a to i64
49 %1 = zext i32 %b to i64
50 %2 = zext i32 %c to i64
51 %3 = zext i32 %d to i64
/external/llvm/test/CodeGen/ARM/
Dfpcmp.ll9 %tmp1 = zext i1 %tmp to i32 ; <i32> [#uses=1]
19 %tmp2 = zext i1 %tmp to i32 ; <i32> [#uses=1]
29 %tmp3 = zext i1 %tmp to i32 ; <i32> [#uses=1]
39 %tmp4 = zext i1 %tmp to i32 ; <i32> [#uses=1]
49 %tmp5 = zext i1 %tmp to i32 ; <i32> [#uses=1]
59 %tmp6 = zext i1 %tmp to i32 ; <i32> [#uses=1]
69 %tmp7 = zext i1 %tmp to i32 ; <i32> [#uses=1]

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