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Searched refs:Cond (Results 1 – 25 of 150) sorted by relevance

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/external/valgrind/main/
Dglibc-2.2.supp21 # Cond (previously known as Value0)
29 Memcheck:Cond
35 Memcheck:Cond
42 Memcheck:Cond
51 elf_dynamic_do_rel.7/_dl_relocate_object_internal/dl_open_worker(Cond)
52 Memcheck:Cond
61 _dl_relocate_object*/*libc-2.2.?.so/_dl_catch_error*(Cond)
62 Memcheck:Cond
69 Memcheck:Cond
74 Memcheck:Cond
[all …]
Dglibc-2.3.supp21 # Cond (previously known as Value0)
28 Memcheck:Cond
34 Memcheck:Cond
41 Memcheck:Cond
47 strlen/*dl_map_object*(Cond)
48 Memcheck:Cond
54 strlen/*dl_open_worker*(Cond)
55 Memcheck:Cond
61 Memcheck:Cond
81 Memcheck:Cond
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Dxfree-4.supp25 # Cond (previously known as Value0)
41 libX11.so.6.2/libX11.so.6.2/libX11.so.6.2(Cond)
42 Memcheck:Cond
49 libXt.so.6.2/libXt.so.6.2/libXt.so.6.2(Cond)
50 Memcheck:Cond
58 libXaw.so.7.0/libXaw.so.7.0/libXaw.so.7.0(Cond)
59 Memcheck:Cond
66 libXmu.so.6.2/libXmu.so.6.2/libXmu.so.6.2(Cond)
67 Memcheck:Cond
74 libXt.so.6.0/libXt.so.6.0/libXaw.so.7.0(Cond)
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Ddarwin9.supp54 macos-Cond-1
55 Memcheck:Cond
62 macos-Cond-2
63 Memcheck:Cond
70 macos-Cond-3
71 Memcheck:Cond
78 macos-Cond-4
79 Memcheck:Cond
86 macos-Cond-5
87 Memcheck:Cond
[all …]
Dglibc-2.4.supp21 # Cond (previously known as Value0)
31 Memcheck:Cond
38 Memcheck:Cond
47 Memcheck:Cond
56 Memcheck:Cond
73 Memcheck:Cond
90 Memcheck:Cond
97 Memcheck:Cond
122 Memcheck:Cond
Dglibc-X.X.supp.in24 # Cond (previously known as Value0)
35 Memcheck:Cond
41 Memcheck:Cond
48 Memcheck:Cond
55 Memcheck:Cond
62 Memcheck:Cond
118 Memcheck:Cond
125 Memcheck:Cond
236 Memcheck:Cond
Dglibc-2.X.supp.in24 # Cond (previously known as Value0)
35 Memcheck:Cond
41 Memcheck:Cond
48 Memcheck:Cond
55 Memcheck:Cond
62 Memcheck:Cond
118 Memcheck:Cond
125 Memcheck:Cond
236 Memcheck:Cond
/external/llvm/lib/Target/MBlaze/
DMBlazeInstrInfo.cpp118 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in AnalyzeBranch()
147 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); in AnalyzeBranch()
166 Cond.push_back(SecondLastInst->getOperand(0)); in AnalyzeBranch()
189 const SmallVectorImpl<MachineOperand> &Cond, in InsertBranch() argument
193 assert((Cond.size() == 2 || Cond.size() == 0) && in InsertBranch()
197 if (!Cond.empty()) in InsertBranch()
198 Opc = (unsigned)Cond[0].getImm(); in InsertBranch()
201 if (Cond.empty()) // Unconditional branch in InsertBranch()
[all …]
/external/clang/test/SemaCXX/
Dvector.cpp40 void conditional(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, in conditional() argument
43 __typeof__(Cond? c16 : c16) *c16p1 = &c16; in conditional()
44 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16; in conditional()
45 __typeof__(Cond? c16e : c16e) *c16ep1 = &c16e; in conditional()
46 __typeof__(Cond? ll16e : ll16e) *ll16ep1 = &ll16e; in conditional()
49 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e; in conditional()
50 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e; in conditional()
51 __typeof__(Cond? ll16 : ll16e) *ll16ep2 = &ll16e; in conditional()
52 __typeof__(Cond? ll16e : ll16) *ll16ep3 = &ll16e; in conditional()
55 (void)(Cond? c16 : ll16); in conditional()
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/external/llvm/lib/Target/Alpha/
DAlphaInstrInfo.cpp91 const SmallVectorImpl<MachineOperand> &Cond, in InsertBranch() argument
94 assert((Cond.size() == 2 || Cond.size() == 0) && in InsertBranch()
99 if (Cond.empty()) // Unconditional branch in InsertBranch()
102 if (isAlphaIntCondCode(Cond[0].getImm())) in InsertBranch()
104 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
107 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
112 if (isAlphaIntCondCode(Cond[0].getImm())) in InsertBranch()
114 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
117 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
221 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
[all …]
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp189 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
222 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
223 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
244 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
245 Cond.push_back(SecondLastInst->getOperand(0)); in AnalyzeBranch()
277 const SmallVectorImpl<MachineOperand> &Cond, in InsertBranch() argument
281 assert((Cond.size() == 2 || Cond.size() == 0) && in InsertBranch()
285 if (Cond.empty()) { in InsertBranch()
290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in InsertBranch()
[all …]
/external/clang/lib/StaticAnalyzer/Core/
DSimpleConstraintManager.cpp60 DefinedSVal Cond, in assume() argument
62 if (isa<NonLoc>(Cond)) in assume()
63 return assume(state, cast<NonLoc>(Cond), Assumption); in assume()
65 return assume(state, cast<Loc>(Cond), Assumption); in assume()
75 Loc Cond, bool Assumption) { in assumeAux() argument
79 switch (Cond.getSubKind()) { in assumeAux()
87 const MemRegion *R = cast<loc::MemRegionVal>(Cond).getRegion(); in assumeAux()
109 bool b = cast<loc::ConcreteInt>(Cond).getValue() != 0; in assumeAux()
139 NonLoc Cond, in assumeAux() argument
144 if (!canReasonAbout(Cond)) { in assumeAux()
[all …]
DSimpleConstraintManager.h36 const GRState *assume(const GRState *state, DefinedSVal Cond,
39 const GRState *assume(const GRState *state, Loc Cond, bool Assumption);
41 const GRState *assume(const GRState *state, NonLoc Cond, bool Assumption);
84 const GRState *assumeAux(const GRState *state, Loc Cond,bool Assumption);
86 const GRState *assumeAux(const GRState *state, NonLoc Cond, bool Assumption);
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp130 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in ReverseBranchCondition()
131 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in ReverseBranchCondition()
133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
159 Cond[0].setImm(CC); in ReverseBranchCondition()
178 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
213 Cond.clear(); in AnalyzeBranch()
237 if (Cond.empty()) { in AnalyzeBranch()
240 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
246 assert(Cond.size() == 1); in AnalyzeBranch()
254 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in AnalyzeBranch()
[all …]
/external/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp264 SmallVectorImpl<MachineOperand>& Cond) { in AnalyzeCondBr() argument
271 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
274 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
280 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
325 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); in AnalyzeBranch()
351 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); in AnalyzeBranch()
359 const SmallVectorImpl<MachineOperand>& Cond) in BuildCondBr()
361 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
365 for (unsigned i = 1; i < Cond.size(); ++i) in BuildCondBr()
366 MIB.addReg(Cond[i].getReg()); in BuildCondBr()
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/external/llvm/test/Transforms/InstCombine/
Dstore.ll28 br i1 %C, label %Cond, label %Cond2
30 Cond:
44 ; CHECK-NEXT: %storemerge = phi i32 [ 47, %Cond2 ], [ -987654321, %Cond ]
52 br i1 %C, label %Cond, label %Cont
54 Cond:
64 ; CHECK-NEXT: %storemerge = phi i32 [ -987654321, %Cond ], [ 47, %0 ]
71 br i1 %C, label %Cond, label %Cont
73 Cond:
Dudiv_select_to_select_shift.ll2 ; udiv X, (Select Cond, C1, C2) --> Select Cond, (shr X, C1), (shr X, C2)
9 define i64 @test(i64 %X, i1 %Cond ) {
11 %divisor1 = select i1 %Cond, i64 16, i64 8
13 %divisor2 = select i1 %Cond, i64 8, i64 0
/external/clang/test/SemaTemplate/
Dvalue-dependent-null-pointer-constant.cpp5 const char *f0(bool Cond) { in f0()
6 return Cond? "honk" : N; in f0()
9 const char *f1(bool Cond) { in f1()
10 return Cond? N : "honk"; in f1()
/external/llvm/lib/Target/CellSPU/
DSPUInstrInfo.cpp215 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
246 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in AnalyzeBranch()
247 Cond.push_back(LastInst->getOperand(0)); in AnalyzeBranch()
267 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); in AnalyzeBranch()
268 Cond.push_back(SecondLastInst->getOperand(0)); in AnalyzeBranch()
351 const SmallVectorImpl<MachineOperand> &Cond, in InsertBranch() argument
355 assert((Cond.size() == 2 || Cond.size() == 0) && in InsertBranch()
370 if (Cond.empty()) { in InsertBranch()
386 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm())); in InsertBranch()
387 MIB.addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
[all …]
/external/llvm/test/Transforms/ADCE/
D2003-11-16-MissingPostDominanceInfo.ll6 br i1 %C, label %Cond, label %Done
8 Cond: ; preds = %0
11 Loop: ; preds = %Loop, %Cond
15 Done: ; preds = %Cond, %0
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp1907 ISD::CondCode Cond, bool foldBooleans, in SimplifySetCC() argument
1912 switch (Cond) { in SimplifySetCC()
1923 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); in SimplifySetCC()
1936 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1938 if ((C1 == 0) == (Cond == ISD::SETEQ)) { in SimplifySetCC()
1941 Cond = ISD::SETNE; in SimplifySetCC()
1945 Cond = ISD::SETEQ; in SimplifySetCC()
1949 Zero, Cond); in SimplifySetCC()
1966 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1970 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp197 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in ReverseBranchCondition()
198 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in ReverseBranchCondition()
200 SystemZCC::CondCodes CC = static_cast<SystemZCC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
201 Cond[0].setImm(getOppositeCondition(CC)); in ReverseBranchCondition()
220 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
249 Cond.clear(); in AnalyzeBranch()
271 if (Cond.empty()) { in AnalyzeBranch()
274 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranch()
280 assert(Cond.size() == 1); in AnalyzeBranch()
288 SystemZCC::CondCodes OldBranchCode = (SystemZCC::CondCodes)Cond[0].getImm(); in AnalyzeBranch()
[all …]
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
DConstraintManager.h36 virtual const GRState *assume(const GRState *state, DefinedSVal Cond,
40 DefinedSVal Cond) { in assumeDual() argument
41 return std::make_pair(assume(state, Cond, true), in assumeDual()
42 assume(state, Cond, false)); in assumeDual()
/external/llvm/lib/CodeGen/
DMachineBasicBlock.cpp287 SmallVector<MachineOperand, 4> Cond; in updateTerminator() local
289 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond); in updateTerminator()
292 if (Cond.empty()) { in updateTerminator()
303 TII->InsertBranch(*this, TBB, 0, Cond, dl); in updateTerminator()
311 if (TII->ReverseBranchCondition(Cond)) in updateTerminator()
314 TII->InsertBranch(*this, FBB, 0, Cond, dl); in updateTerminator()
317 TII->InsertBranch(*this, TBB, 0, Cond, dl); in updateTerminator()
325 if (TII->ReverseBranchCondition(Cond)) { in updateTerminator()
327 Cond.clear(); in updateTerminator()
328 TII->InsertBranch(*this, MBBA, 0, Cond, dl); in updateTerminator()
[all …]
/external/llvm/lib/Target/PTX/
DPTXInstrInfo.cpp174 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranch() argument
219 Cond.push_back(instLast1.getOperand(i)); in AnalyzeBranch()
220 Cond.push_back(instLast1.getOperand(i+1)); in AnalyzeBranch()
236 Cond.push_back(instLast2.getOperand(i)); in AnalyzeBranch()
237 Cond.push_back(instLast2.getOperand(i+1)); in AnalyzeBranch()
263 const SmallVectorImpl<MachineOperand> &Cond, in InsertBranch() argument
272 DEBUG(dbgs() << "InsertBranch: Cond size: " << Cond.size() << "\n"); in InsertBranch()
278 .addMBB(TBB).addReg(Cond[0].getReg()).addImm(Cond[1].getImm()); in InsertBranch()
282 } else if (Cond.size()) { in InsertBranch()
284 .addMBB(TBB).addReg(Cond[0].getReg()).addImm(Cond[1].getImm()); in InsertBranch()

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