1 //===- ARMBaseRegisterInfo.h - ARM Register Information Impl ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef ARMBASEREGISTERINFO_H
15 #define ARMBASEREGISTERINFO_H
16
17 #include "ARM.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19
20 #define GET_REGINFO_HEADER
21 #include "ARMGenRegisterInfo.inc"
22
23 namespace llvm {
24 class ARMSubtarget;
25 class ARMBaseInstrInfo;
26 class Type;
27
28 /// Register allocation hints.
29 namespace ARMRI {
30 enum {
31 RegPairOdd = 1,
32 RegPairEven = 2
33 };
34 }
35
36 /// isARMLowRegister - Returns true if the register is low register r0-r7.
37 ///
isARMLowRegister(unsigned Reg)38 static inline bool isARMLowRegister(unsigned Reg) {
39 using namespace ARM;
40 switch (Reg) {
41 case R0: case R1: case R2: case R3:
42 case R4: case R5: case R6: case R7:
43 return true;
44 default:
45 return false;
46 }
47 }
48
49 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
50 /// or a stack/pc register that we should push/pop.
isARMArea1Register(unsigned Reg,bool isDarwin)51 static inline bool isARMArea1Register(unsigned Reg, bool isDarwin) {
52 using namespace ARM;
53 switch (Reg) {
54 case R0: case R1: case R2: case R3:
55 case R4: case R5: case R6: case R7:
56 case LR: case SP: case PC:
57 return true;
58 case R8: case R9: case R10: case R11:
59 // For darwin we want r7 and lr to be next to each other.
60 return !isDarwin;
61 default:
62 return false;
63 }
64 }
65
isARMArea2Register(unsigned Reg,bool isDarwin)66 static inline bool isARMArea2Register(unsigned Reg, bool isDarwin) {
67 using namespace ARM;
68 switch (Reg) {
69 case R8: case R9: case R10: case R11:
70 // Darwin has this second area.
71 return isDarwin;
72 default:
73 return false;
74 }
75 }
76
isARMArea3Register(unsigned Reg,bool isDarwin)77 static inline bool isARMArea3Register(unsigned Reg, bool isDarwin) {
78 using namespace ARM;
79 switch (Reg) {
80 case D15: case D14: case D13: case D12:
81 case D11: case D10: case D9: case D8:
82 return true;
83 default:
84 return false;
85 }
86 }
87
88 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
89 protected:
90 const ARMBaseInstrInfo &TII;
91 const ARMSubtarget &STI;
92
93 /// FramePtr - ARM physical register used as frame ptr.
94 unsigned FramePtr;
95
96 /// BasePtr - ARM physical register used as a base ptr in complex stack
97 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
98 /// variable size stack objects.
99 unsigned BasePtr;
100
101 // Can be only subclassed.
102 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
103 const ARMSubtarget &STI);
104
105 // Return the opcode that implements 'Op', or 0 if no opcode
106 unsigned getOpcode(int Op) const;
107
108 public:
109 /// Code Generation virtual methods...
110 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
111
112 BitVector getReservedRegs(const MachineFunction &MF) const;
113
114 /// getMatchingSuperRegClass - Return a subclass of the specified register
115 /// class A so that each register in it has a sub-register of the
116 /// specified sub-register index which is in the specified register class B.
117 virtual const TargetRegisterClass *
118 getMatchingSuperRegClass(const TargetRegisterClass *A,
119 const TargetRegisterClass *B, unsigned Idx) const;
120
121 /// canCombineSubRegIndices - Given a register class and a list of
122 /// subregister indices, return true if it's possible to combine the
123 /// subregister indices into one that corresponds to a larger
124 /// subregister. Return the new subregister index by reference. Note the
125 /// new index may be zero if the given subregisters can be combined to
126 /// form the whole register.
127 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
128 SmallVectorImpl<unsigned> &SubIndices,
129 unsigned &NewSubIdx) const;
130
131 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
132
133 const TargetRegisterClass*
134 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
135
136 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
137 MachineFunction &MF) const;
138
139 ArrayRef<unsigned> getRawAllocationOrder(const TargetRegisterClass *RC,
140 unsigned HintType, unsigned HintReg,
141 const MachineFunction &MF) const;
142
143 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
144 const MachineFunction &MF) const;
145
146 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
147 MachineFunction &MF) const;
148
149 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
150
151 bool hasBasePointer(const MachineFunction &MF) const;
152
153 bool canRealignStack(const MachineFunction &MF) const;
154 bool needsStackRealignment(const MachineFunction &MF) const;
155 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
156 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
157 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
158 unsigned BaseReg, int FrameIdx,
159 int64_t Offset) const;
160 void resolveFrameIndex(MachineBasicBlock::iterator I,
161 unsigned BaseReg, int64_t Offset) const;
162 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
163
164 bool cannotEliminateFrame(const MachineFunction &MF) const;
165
166 // Debug information queries.
167 unsigned getFrameRegister(const MachineFunction &MF) const;
getBaseRegister()168 unsigned getBaseRegister() const { return BasePtr; }
169
170 // Exception handling queries.
171 unsigned getEHExceptionRegister() const;
172 unsigned getEHHandlerRegister() const;
173
174 bool isLowRegister(unsigned Reg) const;
175
176
177 /// emitLoadConstPool - Emits a load from constpool to materialize the
178 /// specified immediate.
179 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
180 MachineBasicBlock::iterator &MBBI,
181 DebugLoc dl,
182 unsigned DestReg, unsigned SubIdx,
183 int Val,
184 ARMCC::CondCodes Pred = ARMCC::AL,
185 unsigned PredReg = 0,
186 unsigned MIFlags = MachineInstr::NoFlags)const;
187
188 /// Code Generation virtual methods...
189 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
190
191 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
192
193 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
194
195 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
196
197 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
198 MachineBasicBlock &MBB,
199 MachineBasicBlock::iterator I) const;
200
201 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
202 int SPAdj, RegScavenger *RS = NULL) const;
203
204 private:
205 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
206
207 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
208 };
209
210 } // end namespace llvm
211
212 #endif
213