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1 /*
2  * Copyright (C) Texas Instruments - http://www.ti.com/
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #include <errno.h>
18 #include <malloc.h>
19 #include <stdlib.h>
20 #include <stdarg.h>
21 #include <fcntl.h>
22 #include <poll.h>
23 #include <sys/ioctl.h>
24 #include <linux/fb.h>
25 
26 #include <cutils/properties.h>
27 #include <cutils/log.h>
28 #include <cutils/native_handle.h>
29 #include <hardware/hardware.h>
30 #include <hardware/hwcomposer.h>
31 #include <EGL/egl.h>
32 #include <utils/Timers.h>
33 #include <hardware_legacy/uevent.h>
34 
35 #define ASPECT_RATIO_TOLERANCE 0.02f
36 
37 #ifndef FBIO_WAITFORVSYNC
38 #define FBIO_WAITFORVSYNC	_IOW('F', 0x20, __u32)
39 #endif
40 
41 #define min(a, b) ( { typeof(a) __a = (a), __b = (b); __a < __b ? __a : __b; } )
42 #define max(a, b) ( { typeof(a) __a = (a), __b = (b); __a > __b ? __a : __b; } )
43 #define swap(a, b) do { typeof(a) __a = (a); (a) = (b); (b) = __a; } while (0)
44 
45 #define WIDTH(rect) ((rect).right - (rect).left)
46 #define HEIGHT(rect) ((rect).bottom - (rect).top)
47 
48 #include <video/dsscomp.h>
49 
50 #include "hal_public.h"
51 
52 #define MAX_HW_OVERLAYS 4
53 #define NUM_NONSCALING_OVERLAYS 1
54 #define HAL_PIXEL_FORMAT_BGRX_8888		0x1FF
55 #define HAL_PIXEL_FORMAT_TI_NV12 0x100
56 #define HAL_PIXEL_FORMAT_TI_NV12_PADDED 0x101
57 #define MAX_TILER_SLOT (16 << 20)
58 
59 #define MIN(a,b)		  ((a)<(b)?(a):(b))
60 #define MAX(a,b)		  ((a)>(b)?(a):(b))
61 #define CLAMP(x,low,high) (((x)>(high))?(high):(((x)<(low))?(low):(x)))
62 
63 struct ext_transform_t {
64     __u8 rotation : 3;          /* 90-degree clockwise rotations */
65     __u8 hflip    : 1;          /* flip l-r (after rotation) */
66     __u8 enabled  : 1;          /* cloning enabled */
67     __u8 docking  : 1;          /* docking vs. mirroring - used for state */
68 };
69 
70 /* cloning support and state */
71 struct omap4_hwc_ext {
72     /* support */
73     struct ext_transform_t mirror;      /* mirroring settings */
74     struct ext_transform_t dock;        /* docking settings */
75     __u8 avoid_mode_change;             /* use HDMI mode used for mirroring if possible */
76 
77     /* state */
78     __u8 on_tv;                         /* using a tv */
79     struct ext_transform_t current;     /* current settings */
80     struct ext_transform_t last;        /* last-used settings */
81 
82     /* configuration */
83     __u32 last_xres_used;               /* resolution and pixel ratio used for mode selection */
84     __u32 last_yres_used;
85     __u32 last_mode;                    /* 2-s complement of last HDMI mode set, 0 if none */
86     __u32 mirror_mode;                  /* 2-s complement of mode used when mirroring */
87     float last_xpy;
88     __u16 width;                        /* external screen dimensions */
89     __u16 height;
90     __u32 xres;                         /* external screen resolution */
91     __u32 yres;
92     float m[2][3];                      /* external transformation matrix */
93     hwc_rect_t mirror_region;           /* region of screen to mirror */
94 };
95 typedef struct omap4_hwc_ext omap4_hwc_ext_t;
96 
97 /* used by property settings */
98 enum {
99     EXT_ROTATION    = 3,        /* rotation while mirroring */
100     EXT_HFLIP       = (1 << 2), /* flip l-r on output (after rotation) */
101 };
102 
103 struct omap4_hwc_module {
104     hwc_module_t base;
105 
106     IMG_framebuffer_device_public_t *fb_dev;
107 };
108 typedef struct omap4_hwc_module omap4_hwc_module_t;
109 
110 struct omap4_hwc_device {
111     hwc_composer_device_t base;
112     hwc_procs_t *procs;
113     pthread_t hdmi_thread;
114     pthread_mutex_t lock;
115     int dsscomp_fd;
116     int fb_fd;
117     int hdmi_fb_fd;
118     int pipe_fds[2];
119 
120     IMG_framebuffer_device_public_t *fb_dev;
121     struct dsscomp_setup_dispc_data dsscomp_data;
122     struct dsscomp_display_info fb_dis;
123 
124     omap4_hwc_ext_t ext;           /* external mirroring data */
125 
126     buffer_handle_t *buffers;
127     int use_sgx;
128     int swap_rb;
129     unsigned int post2_layers;
130     int last_ext_ovls;
131     int last_int_ovls;
132     int ext_ovls;
133     int ext_ovls_wanted;
134 
135     int flags_rgb_order;
136     int flags_nv12_only;
137     int idle;
138 
139     int force_sgx;
140 };
141 typedef struct omap4_hwc_device omap4_hwc_device_t;
142 
143 static int debug = 0;
144 
dump_layer(hwc_layer_t const * l)145 static void dump_layer(hwc_layer_t const* l)
146 {
147     LOGD("\ttype=%d, flags=%08x, handle=%p, tr=%02x, blend=%04x, {%d,%d,%d,%d}, {%d,%d,%d,%d}",
148             l->compositionType, l->flags, l->handle, l->transform, l->blending,
149             l->sourceCrop.left,
150             l->sourceCrop.top,
151             l->sourceCrop.right,
152             l->sourceCrop.bottom,
153             l->displayFrame.left,
154             l->displayFrame.top,
155             l->displayFrame.right,
156             l->displayFrame.bottom);
157 }
158 
dump_dsscomp(struct dsscomp_setup_dispc_data * d)159 static void dump_dsscomp(struct dsscomp_setup_dispc_data *d)
160 {
161     unsigned i;
162 
163     LOGD("[%08x] set: %c%c%c %d ovls\n",
164          d->sync_id,
165          (d->mode & DSSCOMP_SETUP_MODE_APPLY) ? 'A' : '-',
166          (d->mode & DSSCOMP_SETUP_MODE_DISPLAY) ? 'D' : '-',
167          (d->mode & DSSCOMP_SETUP_MODE_CAPTURE) ? 'C' : '-',
168          d->num_ovls);
169 
170     for (i = 0; i < d->num_mgrs; i++) {
171         struct dss2_mgr_info *mi = d->mgrs + i;
172         LOGD(" (dis%d alpha=%d col=%08x ilace=%d)\n",
173             mi->ix,
174             mi->alpha_blending, mi->default_color,
175             mi->interlaced);
176     }
177 
178     for (i = 0; i < d->num_ovls; i++) {
179             struct dss2_ovl_info *oi = d->ovls + i;
180             struct dss2_ovl_cfg *c = &oi->cfg;
181             if (c->zonly)
182                     LOGE("ovl%d(%s z%d)\n",
183                          c->ix, c->enabled ? "ON" : "off", c->zorder);
184             else
185                     LOGE("ovl%d(%s z%d %x%s *%d%% %d*%d:%d,%d+%d,%d rot%d%s => %d,%d+%d,%d %p/%p|%d)\n",
186                          c->ix, c->enabled ? "ON" : "off", c->zorder, c->color_mode,
187                          c->pre_mult_alpha ? " premult" : "",
188                          (c->global_alpha * 100 + 128) / 255,
189                          c->width, c->height, c->crop.x, c->crop.y,
190                          c->crop.w, c->crop.h,
191                          c->rotation, c->mirror ? "+mir" : "",
192                          c->win.x, c->win.y, c->win.w, c->win.h,
193                          (void *) oi->ba, (void *) oi->uv, c->stride);
194     }
195 }
196 
omap4_hwc_is_valid_format(int format)197 static int omap4_hwc_is_valid_format(int format)
198 {
199     switch(format) {
200     case HAL_PIXEL_FORMAT_RGB_565:
201     case HAL_PIXEL_FORMAT_RGBX_8888:
202     case HAL_PIXEL_FORMAT_RGBA_8888:
203     case HAL_PIXEL_FORMAT_BGRA_8888:
204     case HAL_PIXEL_FORMAT_BGRX_8888:
205     case HAL_PIXEL_FORMAT_TI_NV12:
206     case HAL_PIXEL_FORMAT_TI_NV12_PADDED:
207         return 1;
208 
209     default:
210         return 0;
211     }
212 }
213 
scaled(hwc_layer_t * layer)214 static int scaled(hwc_layer_t *layer)
215 {
216     int w = WIDTH(layer->sourceCrop);
217     int h = HEIGHT(layer->sourceCrop);
218 
219     if (layer->transform & HWC_TRANSFORM_ROT_90)
220         swap(w, h);
221 
222     return WIDTH(layer->displayFrame) != w || HEIGHT(layer->displayFrame) != h;
223 }
224 
isprotected(hwc_layer_t * layer)225 static int isprotected(hwc_layer_t *layer)
226 {
227     IMG_native_handle_t *handle = (IMG_native_handle_t *)layer->handle;
228 
229     return (handle->usage & GRALLOC_USAGE_PROTECTED);
230 }
231 
232 static int sync_id = 0;
233 
234 #define is_BLENDED(blending) ((blending) != HWC_BLENDING_NONE)
235 
236 #define is_RGB(format) ((format) == HAL_PIXEL_FORMAT_BGRA_8888 || (format) == HAL_PIXEL_FORMAT_RGB_565 || (format) == HAL_PIXEL_FORMAT_BGRX_8888)
237 #define is_BGR(format) ((format) == HAL_PIXEL_FORMAT_RGBX_8888 || (format) == HAL_PIXEL_FORMAT_RGBA_8888)
238 #define is_NV12(format) ((format) == HAL_PIXEL_FORMAT_TI_NV12 || (format) == HAL_PIXEL_FORMAT_TI_NV12_PADDED)
239 
dockable(hwc_layer_t * layer)240 static int dockable(hwc_layer_t *layer)
241 {
242     IMG_native_handle_t *handle = (IMG_native_handle_t *)layer->handle;
243 
244     return (handle->usage & GRALLOC_USAGE_EXTERNAL_DISP);
245 }
246 
mem1d(IMG_native_handle_t * handle)247 static unsigned int mem1d(IMG_native_handle_t *handle)
248 {
249     if (handle == NULL)
250             return 0;
251 
252     int bpp = is_NV12(handle->iFormat) ? 0 : (handle->iFormat == HAL_PIXEL_FORMAT_RGB_565 ? 2 : 4);
253     int stride = ALIGN(handle->iWidth, HW_ALIGN) * bpp;
254     return stride * handle->iHeight;
255 }
256 
257 static void
omap4_hwc_setup_layer_base(struct dss2_ovl_cfg * oc,int index,int format,int width,int height)258 omap4_hwc_setup_layer_base(struct dss2_ovl_cfg *oc, int index, int format, int width, int height)
259 {
260     unsigned int bits_per_pixel;
261 
262     /* YUV2RGB conversion */
263     const struct omap_dss_cconv_coefs ctbl_bt601_5 = {
264         298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
265     };
266 
267     /* convert color format */
268     switch (format) {
269     case HAL_PIXEL_FORMAT_RGBX_8888:
270         /* Should be XBGR32, but this isn't supported */
271         oc->color_mode = OMAP_DSS_COLOR_RGB24U;
272         bits_per_pixel = 32;
273         break;
274 
275     case HAL_PIXEL_FORMAT_RGBA_8888:
276         /* Should be ABGR32, but this isn't supported */
277         oc->color_mode = OMAP_DSS_COLOR_ARGB32;
278         bits_per_pixel = 32;
279         break;
280 
281     case HAL_PIXEL_FORMAT_BGRA_8888:
282         oc->color_mode = OMAP_DSS_COLOR_ARGB32;
283         bits_per_pixel = 32;
284         break;
285 
286     case HAL_PIXEL_FORMAT_BGRX_8888:
287         oc->color_mode = OMAP_DSS_COLOR_RGB24U;
288         bits_per_pixel = 32;
289         break;
290 
291     case HAL_PIXEL_FORMAT_RGB_565:
292         oc->color_mode = OMAP_DSS_COLOR_RGB16;
293         bits_per_pixel = 16;
294         break;
295 
296     case HAL_PIXEL_FORMAT_TI_NV12:
297     case HAL_PIXEL_FORMAT_TI_NV12_PADDED:
298         oc->color_mode = OMAP_DSS_COLOR_NV12;
299         bits_per_pixel = 8;
300         oc->cconv = ctbl_bt601_5;
301         break;
302 
303     default:
304         /* Should have been filtered out */
305         LOGV("Unsupported pixel format");
306         return;
307     }
308 
309     oc->width = width;
310     oc->height = height;
311     oc->stride = ALIGN(width, HW_ALIGN) * bits_per_pixel / 8;
312 
313     oc->enabled = 1;
314     oc->global_alpha = 255;
315     oc->zorder = index;
316     oc->ix = 0;
317 
318     /* defaults for SGX framebuffer renders */
319     oc->crop.w = oc->win.w = width;
320     oc->crop.h = oc->win.h = height;
321 
322     /* for now interlacing and vc1 info is not supplied */
323     oc->ilace = OMAP_DSS_ILACE_NONE;
324     oc->vc1.enable = 0;
325 }
326 
327 static void
omap4_hwc_setup_layer(omap4_hwc_device_t * hwc_dev,struct dss2_ovl_info * ovl,hwc_layer_t * layer,int index,int format,int width,int height)328 omap4_hwc_setup_layer(omap4_hwc_device_t *hwc_dev, struct dss2_ovl_info *ovl,
329                       hwc_layer_t *layer, int index,
330                       int format, int width, int height)
331 {
332     struct dss2_ovl_cfg *oc = &ovl->cfg;
333 
334     //dump_layer(layer);
335 
336     if (format == HAL_PIXEL_FORMAT_BGRA_8888 && !is_BLENDED(layer->blending)) {
337         format = HAL_PIXEL_FORMAT_BGRX_8888;
338     }
339 
340     omap4_hwc_setup_layer_base(oc, index, format, width, height);
341 
342     /* convert transformation - assuming 0-set config */
343     if (layer->transform & HWC_TRANSFORM_FLIP_H)
344         oc->mirror = 1;
345     if (layer->transform & HWC_TRANSFORM_FLIP_V) {
346         oc->rotation = 2;
347         oc->mirror = !oc->mirror;
348     }
349     if (layer->transform & HWC_TRANSFORM_ROT_90) {
350         oc->rotation += oc->mirror ? -1 : 1;
351         oc->rotation &= 3;
352     }
353 
354     oc->pre_mult_alpha = layer->blending == HWC_BLENDING_PREMULT;
355 
356     /* display position */
357     oc->win.x = layer->displayFrame.left;
358     oc->win.y = layer->displayFrame.top;
359     oc->win.w = WIDTH(layer->displayFrame);
360     oc->win.h = HEIGHT(layer->displayFrame);
361 
362     /* crop */
363     oc->crop.x = layer->sourceCrop.left;
364     oc->crop.y = layer->sourceCrop.top;
365     oc->crop.w = WIDTH(layer->sourceCrop);
366     oc->crop.h = HEIGHT(layer->sourceCrop);
367 }
368 
369 const float m_unit[2][3] = { { 1., 0., 0. }, { 0., 1., 0. } };
370 
m_translate(float m[2][3],int dx,int dy)371 static inline void m_translate(float m[2][3], int dx, int dy)
372 {
373     m[0][2] += dx;
374     m[1][2] += dy;
375 }
376 
m_scale1(float m[3],int from,int to)377 static inline void m_scale1(float m[3], int from, int to)
378 {
379     m[0] = m[0] * to / from;
380     m[1] = m[1] * to / from;
381     m[2] = m[2] * to / from;
382 }
383 
m_scale(float m[2][3],int x_from,int x_to,int y_from,int y_to)384 static inline void m_scale(float m[2][3], int x_from, int x_to, int y_from, int y_to)
385 {
386     m_scale1(m[0], x_from, x_to);
387     m_scale1(m[1], y_from, y_to);
388 }
389 
m_rotate(float m[2][3],int quarter_turns)390 static void m_rotate(float m[2][3], int quarter_turns)
391 {
392     if (quarter_turns & 2)
393         m_scale(m, 1, -1, 1, -1);
394     if (quarter_turns & 1) {
395         int q;
396         q = m[0][0]; m[0][0] = -m[1][0]; m[1][0] = q;
397         q = m[0][1]; m[0][1] = -m[1][1]; m[1][1] = q;
398         q = m[0][2]; m[0][2] = -m[1][2]; m[1][2] = q;
399     }
400 }
401 
m_round(float x)402 static inline int m_round(float x)
403 {
404     /* int truncates towards 0 */
405     return (int) (x < 0 ? x - 0.5 : x + 0.5);
406 }
407 
408 /*
409  * assuming xpy (xratio:yratio) original pixel ratio, calculate the adjusted width
410  * and height for a screen of xres/yres and physical size of width/height.
411  * The adjusted size is the largest that fits into the screen.
412  */
get_max_dimensions(__u32 orig_xres,__u32 orig_yres,float xpy,__u32 scr_xres,__u32 scr_yres,__u32 scr_width,__u32 scr_height,__u32 * adj_xres,__u32 * adj_yres)413 static void get_max_dimensions(__u32 orig_xres, __u32 orig_yres,
414                                float xpy,
415                                __u32 scr_xres, __u32 scr_yres,
416                                __u32 scr_width, __u32 scr_height,
417                                __u32 *adj_xres, __u32 *adj_yres)
418 {
419     /* assume full screen (largest size)*/
420     *adj_xres = scr_xres;
421     *adj_yres = scr_yres;
422 
423     /* assume 1:1 pixel ratios if none supplied */
424     if (!scr_width || !scr_height) {
425         scr_width = scr_xres;
426         scr_height = scr_yres;
427     }
428 
429     /* trim to keep aspect ratio */
430     float x_factor = orig_xres * xpy * scr_height;
431     float y_factor = orig_yres *       scr_width;
432 
433     /* allow for tolerance so we avoid scaling if framebuffer is standard size */
434     if (x_factor < y_factor * (1.f - ASPECT_RATIO_TOLERANCE))
435         *adj_xres = (__u32) (x_factor * *adj_xres / y_factor + 0.5);
436     else if (x_factor * (1.f - ASPECT_RATIO_TOLERANCE) > y_factor)
437         *adj_yres = (__u32) (y_factor * *adj_yres / x_factor + 0.5);
438 }
439 
set_ext_matrix(omap4_hwc_ext_t * ext,struct hwc_rect region)440 static void set_ext_matrix(omap4_hwc_ext_t *ext, struct hwc_rect region)
441 {
442     int orig_w = WIDTH(region);
443     int orig_h = HEIGHT(region);
444 
445     /* assume 1:1 lcd pixel ratio */
446     float xpy = 1.;
447 
448     /* reorientation matrix is:
449        m = (center-from-target-center) * (scale-to-target) * (mirror) * (rotate) * (center-to-original-center) */
450 
451     memcpy(ext->m, m_unit, sizeof(m_unit));
452     m_translate(ext->m, -(orig_w >> 1) - region.left, -(orig_h >> 1) - region.top);
453     m_rotate(ext->m, ext->current.rotation);
454     if (ext->current.hflip)
455         m_scale(ext->m, 1, -1, 1, 1);
456 
457     if (ext->current.rotation & 1) {
458         swap(orig_w, orig_h);
459         xpy = 1. / xpy;
460     }
461 
462     /* get target size */
463     __u32 adj_xres, adj_yres;
464     get_max_dimensions(orig_w, orig_h, xpy,
465                        ext->xres, ext->yres, ext->width, ext->height,
466                        &adj_xres, &adj_yres);
467 
468     m_scale(ext->m, orig_w, adj_xres, orig_h, adj_yres);
469     m_translate(ext->m, ext->xres >> 1, ext->yres >> 1);
470 }
471 
472 static void
omap4_hwc_create_ext_matrix(omap4_hwc_ext_t * ext)473 omap4_hwc_create_ext_matrix(omap4_hwc_ext_t *ext)
474 {
475     /* use VGA external resolution as default */
476     if (!ext->xres ||
477         !ext->yres) {
478         ext->xres = 640;
479         ext->yres = 480;
480     }
481 
482     /* if docking, we cannot create the matrix ahead of time as it depends on input size */
483     if (ext->mirror.enabled) {
484         ext->current = ext->mirror;
485         set_ext_matrix(ext, ext->mirror_region);
486     }
487 }
488 
489 static int
crop_to_rect(struct dss2_ovl_cfg * cfg,struct hwc_rect vis_rect)490 crop_to_rect(struct dss2_ovl_cfg *cfg, struct hwc_rect vis_rect)
491 {
492     struct {
493         int xy[2];
494         int wh[2];
495     } crop, win;
496     struct {
497         int lt[2];
498         int rb[2];
499     } vis;
500     win.xy[0] = cfg->win.x; win.xy[1] = cfg->win.y;
501     win.wh[0] = cfg->win.w; win.wh[1] = cfg->win.h;
502     crop.xy[0] = cfg->crop.x; crop.xy[1] = cfg->crop.y;
503     crop.wh[0] = cfg->crop.w; crop.wh[1] = cfg->crop.h;
504     vis.lt[0] = vis_rect.left; vis.lt[1] = vis_rect.top;
505     vis.rb[0] = vis_rect.right; vis.rb[1] = vis_rect.bottom;
506 
507     int c, swap = cfg->rotation & 1;
508 
509     /* align crop window with display coordinates */
510     if (swap)
511         crop.xy[1] -= (crop.wh[1] = -crop.wh[1]);
512     if (cfg->rotation & 2)
513         crop.xy[!swap] -= (crop.wh[!swap] = -crop.wh[!swap]);
514     if ((!cfg->mirror) ^ !(cfg->rotation & 2))
515         crop.xy[swap] -= (crop.wh[swap] = -crop.wh[swap]);
516 
517     for (c = 0; c < 2; c++) {
518         /* see if complete buffer is outside the vis or it is
519           fully cropped or scaled to 0 */
520         if (win.wh[c] <= 0 || vis.rb[c] <= vis.lt[c] ||
521             win.xy[c] + win.wh[c] <= vis.lt[c] ||
522             win.xy[c] >= vis.rb[c] ||
523             !crop.wh[c ^ swap])
524             return -ENOENT;
525 
526         /* crop left/top */
527         if (win.xy[c] < vis.lt[c]) {
528             /* correction term */
529             int a = (vis.lt[c] - win.xy[c]) * crop.wh[c ^ swap] / win.wh[c];
530             crop.xy[c ^ swap] += a;
531             crop.wh[c ^ swap] -= a;
532             win.wh[c] -= vis.lt[c] - win.xy[c];
533             win.xy[c] = vis.lt[c];
534         }
535         /* crop right/bottom */
536         if (win.xy[c] + win.wh[c] > vis.rb[c]) {
537             crop.wh[c ^ swap] = crop.wh[c ^ swap] * (vis.rb[c] - win.xy[c]) / win.wh[c];
538             win.wh[c] = vis.rb[c] - win.xy[c];
539         }
540 
541         if (!crop.wh[c ^ swap] || !win.wh[c])
542             return -ENOENT;
543     }
544 
545     /* realign crop window to buffer coordinates */
546     if (cfg->rotation & 2)
547         crop.xy[!swap] -= (crop.wh[!swap] = -crop.wh[!swap]);
548     if ((!cfg->mirror) ^ !(cfg->rotation & 2))
549         crop.xy[swap] -= (crop.wh[swap] = -crop.wh[swap]);
550     if (swap)
551         crop.xy[1] -= (crop.wh[1] = -crop.wh[1]);
552 
553     cfg->win.x = win.xy[0]; cfg->win.y = win.xy[1];
554     cfg->win.w = win.wh[0]; cfg->win.h = win.wh[1];
555     cfg->crop.x = crop.xy[0]; cfg->crop.y = crop.xy[1];
556     cfg->crop.w = crop.wh[0]; cfg->crop.h = crop.wh[1];
557 
558     return 0;
559 }
560 
561 static void
omap4_hwc_adjust_ext_layer(omap4_hwc_ext_t * ext,struct dss2_ovl_info * ovl)562 omap4_hwc_adjust_ext_layer(omap4_hwc_ext_t *ext, struct dss2_ovl_info *ovl)
563 {
564     struct dss2_ovl_cfg *oc = &ovl->cfg;
565     float x, y, w, h;
566 
567     /* crop to clone region if mirroring */
568     if (!ext->current.docking &&
569         crop_to_rect(&ovl->cfg, ext->mirror_region) != 0) {
570         ovl->cfg.enabled = 0;
571         return;
572     }
573 
574     /* display position */
575     x = ext->m[0][0] * oc->win.x + ext->m[0][1] * oc->win.y + ext->m[0][2];
576     y = ext->m[1][0] * oc->win.x + ext->m[1][1] * oc->win.y + ext->m[1][2];
577     w = ext->m[0][0] * oc->win.w + ext->m[0][1] * oc->win.h;
578     h = ext->m[1][0] * oc->win.w + ext->m[1][1] * oc->win.h;
579     oc->win.x = m_round(w > 0 ? x : x + w);
580     oc->win.y = m_round(h > 0 ? y : y + h);
581     oc->win.w = m_round(w > 0 ? w : -w);
582     oc->win.h = m_round(h > 0 ? h : -h);
583 
584     /* combining transformations: F^a*R^b*F^i*R^j = F^(a+b)*R^(j+b*(-1)^i), because F*R = R^(-1)*F */
585     oc->rotation += (oc->mirror ? -1 : 1) * ext->current.rotation;
586     oc->rotation &= 3;
587     if (ext->current.hflip)
588         oc->mirror = !oc->mirror;
589 }
590 
591 static struct dsscomp_dispc_limitations {
592     __u8 max_xdecim_2d;
593     __u8 max_ydecim_2d;
594     __u8 max_xdecim_1d;
595     __u8 max_ydecim_1d;
596     __u32 fclk;
597     __u8 max_downscale;
598     __u8 min_width;
599     __u16 integer_scale_ratio_limit;
600 } limits = {
601     .max_xdecim_1d = 16,
602     .max_xdecim_2d = 16,
603     .max_ydecim_1d = 16,
604     .max_ydecim_2d = 2,
605     .fclk = 170666666,
606     .max_downscale = 4,
607     .min_width = 2,
608     .integer_scale_ratio_limit = 2048,
609 };
610 
omap4_hwc_can_scale(int src_w,int src_h,int dst_w,int dst_h,int is_2d,struct dsscomp_display_info * dis,struct dsscomp_dispc_limitations * limits,__u32 pclk)611 static int omap4_hwc_can_scale(int src_w, int src_h, int dst_w, int dst_h, int is_2d,
612                                struct dsscomp_display_info *dis, struct dsscomp_dispc_limitations *limits,
613                                __u32 pclk)
614 {
615     __u32 fclk = limits->fclk / 1000;
616 
617     /* ERRATAs */
618     /* cannot render 1-width layers on DSI video mode panels - we just disallow all 1-width LCD layers */
619     if (dis->channel != OMAP_DSS_CHANNEL_DIGIT && dst_w < limits->min_width)
620         return 0;
621 
622     /* NOTE: no support for checking YUV422 layers that are tricky to scale */
623 
624     /* max downscale */
625     if (dst_h < src_h / limits->max_downscale / (is_2d ? limits->max_ydecim_2d : limits->max_ydecim_1d))
626         return 0;
627 
628     /* for manual panels pclk is 0, and there are no pclk based scaling limits */
629     if (!pclk)
630         return (dst_w < src_w / limits->max_downscale / (is_2d ? limits->max_xdecim_2d : limits->max_xdecim_1d));
631 
632     /* :HACK: limit horizontal downscale well below theoretical limit as we saw display artifacts */
633     if (dst_w < src_w / 4)
634         return 0;
635 
636     /* max horizontal downscale is 4, or the fclk/pixclk */
637     if (fclk > pclk * limits->max_downscale)
638         fclk = pclk * limits->max_downscale;
639     /* for small parts, we need to use integer fclk/pixclk */
640     if (src_w < limits->integer_scale_ratio_limit)
641         fclk = fclk / pclk * pclk;
642     if (dst_w < src_w * pclk / fclk / (is_2d ? limits->max_xdecim_2d : limits->max_xdecim_1d))
643         return 0;
644 
645     return 1;
646 }
647 
omap4_hwc_can_scale_layer(omap4_hwc_device_t * hwc_dev,hwc_layer_t * layer,IMG_native_handle_t * handle)648 static int omap4_hwc_can_scale_layer(omap4_hwc_device_t *hwc_dev, hwc_layer_t *layer, IMG_native_handle_t *handle)
649 {
650     int src_w = WIDTH(layer->sourceCrop);
651     int src_h = HEIGHT(layer->sourceCrop);
652     int dst_w = WIDTH(layer->displayFrame);
653     int dst_h = HEIGHT(layer->displayFrame);
654 
655     /* account for 90-degree rotation */
656     if (layer->transform & HWC_TRANSFORM_ROT_90)
657         swap(src_w, src_h);
658 
659     /* NOTE: layers should be able to be scaled externally since
660        framebuffer is able to be scaled on selected external resolution */
661     return omap4_hwc_can_scale(src_w, src_h, dst_w, dst_h, is_NV12(handle->iFormat), &hwc_dev->fb_dis, &limits,
662                                hwc_dev->fb_dis.timings.pixel_clock);
663 }
664 
omap4_hwc_is_valid_layer(omap4_hwc_device_t * hwc_dev,hwc_layer_t * layer,IMG_native_handle_t * handle)665 static int omap4_hwc_is_valid_layer(omap4_hwc_device_t *hwc_dev,
666                                     hwc_layer_t *layer,
667                                     IMG_native_handle_t *handle)
668 {
669     /* Skip layers are handled by SF */
670     if ((layer->flags & HWC_SKIP_LAYER) || !handle)
671         return 0;
672 
673     if (!omap4_hwc_is_valid_format(handle->iFormat))
674         return 0;
675 
676     /* 1D buffers: no transform, must fit in TILER slot */
677     if (!is_NV12(handle->iFormat)) {
678         if (layer->transform)
679             return 0;
680         if (mem1d(handle) > MAX_TILER_SLOT)
681             return 0;
682     }
683 
684     return omap4_hwc_can_scale_layer(hwc_dev, layer, handle);
685 }
686 
omap4_hwc_set_best_hdmi_mode(omap4_hwc_device_t * hwc_dev,__u32 xres,__u32 yres,float xpy)687 static int omap4_hwc_set_best_hdmi_mode(omap4_hwc_device_t *hwc_dev, __u32 xres, __u32 yres,
688                                         float xpy)
689 {
690     struct _qdis {
691         struct dsscomp_display_info dis;
692         struct dsscomp_videomode modedb[16];
693     } d = { .dis = { .ix = 1 } };
694     omap4_hwc_ext_t *ext = &hwc_dev->ext;
695 
696     d.dis.modedb_len = sizeof(d.modedb) / sizeof(*d.modedb);
697     int ret = ioctl(hwc_dev->dsscomp_fd, DSSCOMP_QUERY_DISPLAY, &d);
698     if (ret)
699         return ret;
700 
701     if (d.dis.timings.x_res * d.dis.timings.y_res == 0 ||
702         xres * yres == 0)
703         return -EINVAL;
704 
705     __u32 i, best = ~0, best_score = 0;
706     ext->width = d.dis.width_in_mm;
707     ext->height = d.dis.height_in_mm;
708     ext->xres = d.dis.timings.x_res;
709     ext->yres = d.dis.timings.y_res;
710     __u32 ext_fb_xres, ext_fb_yres;
711     for (i = 0; i < d.dis.modedb_len; i++) {
712         __u32 score = 0;
713         __u32 area = xres * yres;
714         __u32 mode_area = d.modedb[i].xres * d.modedb[i].yres;
715         __u32 ext_width = d.dis.width_in_mm;
716         __u32 ext_height = d.dis.height_in_mm;
717 
718         if (d.modedb[i].flag & FB_FLAG_RATIO_4_3) {
719             ext_width = 4;
720             ext_height = 3;
721         } else if (d.modedb[i].flag & FB_FLAG_RATIO_16_9) {
722             ext_width = 16;
723             ext_height = 9;
724         }
725 
726         if (mode_area == 0)
727             continue;
728 
729         get_max_dimensions(xres, yres, xpy, d.modedb[i].xres, d.modedb[i].yres,
730                            ext_width, ext_height, &ext_fb_xres, &ext_fb_yres);
731 
732         /* we need to ensure that even TILER2D buffers can be scaled */
733         if (!d.modedb[i].pixclock ||
734             d.modedb[i].vmode ||
735             !omap4_hwc_can_scale(xres, yres, ext_fb_xres, ext_fb_yres,
736                                  1, &d.dis, &limits,
737                                  1000000000 / d.modedb[i].pixclock))
738             continue;
739 
740         /* prefer CEA modes */
741         if (d.modedb[i].flag & (FB_FLAG_RATIO_4_3 | FB_FLAG_RATIO_16_9))
742             score = 1;
743 
744         /* prefer to upscale (1% tolerance) */
745         __u32 upscaling = (ext_fb_xres >= xres * 99 / 100 && ext_fb_yres >= yres * 99 / 100);
746         score = (score << 1) | upscaling;
747 
748         /* prefer the same mode as we use for mirroring to avoid mode change */
749         score = (score << 1) | (i == ~ext->mirror_mode && ext->avoid_mode_change);
750 
751         /* pick closest screen size */
752         if (ext_fb_xres * ext_fb_yres > area)
753             score = (score << 5) | (16 * area / ext_fb_xres / ext_fb_yres);
754         else
755             score = (score << 5) | (16 * ext_fb_xres * ext_fb_yres / area);
756 
757         /* pick smallest leftover area */
758         score = (score << 5) | ((16 * ext_fb_xres * ext_fb_yres + (mode_area >> 1)) / mode_area);
759 
760         /* pick highest frame rate */
761         score = (score << 8) | d.modedb[i].refresh;
762 
763         LOGD("#%d: %dx%d %dHz", i, d.modedb[i].xres, d.modedb[i].yres, d.modedb[i].refresh);
764         if (debug)
765             LOGD("  score=%u adj.res=%dx%d", score, ext_fb_xres, ext_fb_yres);
766         if (best_score < score) {
767             ext->width = ext_width;
768             ext->height = ext_height;
769             ext->xres = d.modedb[i].xres;
770             ext->yres = d.modedb[i].yres;
771             best = i;
772             best_score = score;
773         }
774     }
775     if (~best) {
776         struct dsscomp_setup_display_data sdis = { .ix = 1, };
777         sdis.mode = d.dis.modedb[best];
778         LOGD("picking #%d", best);
779         /* only reconfigure on change */
780         if (ext->last_mode != ~best)
781             ioctl(hwc_dev->dsscomp_fd, DSSCOMP_SETUP_DISPLAY, &sdis);
782         ext->last_mode = ~best;
783     } else {
784         __u32 ext_width = d.dis.width_in_mm;
785         __u32 ext_height = d.dis.height_in_mm;
786         __u32 ext_fb_xres, ext_fb_yres;
787 
788         get_max_dimensions(xres, yres, xpy, d.dis.timings.x_res, d.dis.timings.y_res,
789                            ext_width, ext_height, &ext_fb_xres, &ext_fb_yres);
790         if (!d.dis.timings.pixel_clock ||
791             d.dis.mgr.interlaced ||
792             !omap4_hwc_can_scale(xres, yres, ext_fb_xres, ext_fb_yres,
793                                  1, &d.dis, &limits,
794                                  d.dis.timings.pixel_clock)) {
795             LOGE("DSS scaler cannot support HDMI cloning");
796             return -1;
797         }
798     }
799     ext->last_xres_used = xres;
800     ext->last_yres_used = yres;
801     ext->last_xpy = xpy;
802     if (d.dis.channel == OMAP_DSS_CHANNEL_DIGIT)
803         ext->on_tv = 1;
804     return 0;
805 }
806 
807 struct counts {
808     unsigned int possible_overlay_layers;
809     unsigned int composited_layers;
810     unsigned int scaled_layers;
811     unsigned int RGB;
812     unsigned int BGR;
813     unsigned int NV12;
814     unsigned int dockable;
815     unsigned int displays;
816     unsigned int max_hw_overlays;
817     unsigned int max_scaling_overlays;
818     unsigned int mem;
819 };
820 
can_dss_render_all(omap4_hwc_device_t * hwc_dev,struct counts * num)821 static inline int can_dss_render_all(omap4_hwc_device_t *hwc_dev, struct counts *num)
822 {
823     omap4_hwc_ext_t *ext = &hwc_dev->ext;
824     int nonscaling_ovls = NUM_NONSCALING_OVERLAYS;
825     num->max_hw_overlays = MAX_HW_OVERLAYS;
826 
827     /*
828      * We cannot atomically switch overlays from one display to another.  First, they
829      * have to be disabled, and the disabling has to take effect on the current display.
830      * We keep track of the available number of overlays here.
831      */
832     if (ext->dock.enabled && !(ext->mirror.enabled && !num->dockable)) {
833         /* some overlays may already be used by the external display, so we account for this */
834 
835         /* reserve just a video pipeline for HDMI if docking */
836         hwc_dev->ext_ovls = num->dockable ? 1 : 0;
837         num->max_hw_overlays -= max(hwc_dev->ext_ovls, hwc_dev->last_ext_ovls);
838 
839         /* use mirroring transform if we are auto-switching to docking mode while mirroring*/
840         if (ext->mirror.enabled) {
841             ext->current = ext->mirror;
842             ext->current.docking = 1;
843         } else {
844             ext->current = ext->dock;
845         }
846     } else if (ext->mirror.enabled) {
847         /*
848          * otherwise, manage just from half the pipelines.  NOTE: there is
849          * no danger of having used too many overlays for external display here.
850          */
851         num->max_hw_overlays >>= 1;
852         nonscaling_ovls >>= 1;
853         hwc_dev->ext_ovls = MAX_HW_OVERLAYS - num->max_hw_overlays;
854         ext->current = ext->mirror;
855     } else {
856         num->max_hw_overlays -= hwc_dev->last_ext_ovls;
857         hwc_dev->ext_ovls = 0;
858         ext->current.enabled = 0;
859     }
860 
861     /*
862      * :TRICKY: We may not have enough overlays on the external display.  We "reserve" them
863      * here to figure out if mirroring is supported, but may not do mirroring for the first
864      * frame while the overlays required for it are cleared.
865      */
866     hwc_dev->ext_ovls_wanted = hwc_dev->ext_ovls;
867     hwc_dev->ext_ovls = min(MAX_HW_OVERLAYS - hwc_dev->last_int_ovls, hwc_dev->ext_ovls);
868 
869     /* if mirroring, we are limited by both internal and external overlays.  However,
870        ext_ovls is always <= MAX_HW_OVERLAYS / 2 <= max_hw_overlays */
871     if (hwc_dev->ext_ovls && ext->current.enabled && !ext->current.docking)
872          num->max_hw_overlays = hwc_dev->ext_ovls;
873 
874     num->max_scaling_overlays = num->max_hw_overlays - nonscaling_ovls;
875 
876     int on_tv = hwc_dev->ext.on_tv;
877     int tform = hwc_dev->ext.current.enabled && (hwc_dev->ext.current.rotation || hwc_dev->ext.current.hflip);
878 
879     return  /* must have at least one layer if using composition bypass to get sync object */
880             num->possible_overlay_layers &&
881             num->possible_overlay_layers <= num->max_hw_overlays &&
882             num->possible_overlay_layers == num->composited_layers &&
883             num->scaled_layers <= num->max_scaling_overlays &&
884             num->NV12 <= num->max_scaling_overlays &&
885             /* fits into TILER slot */
886             num->mem <= MAX_TILER_SLOT &&
887             /* we cannot clone non-NV12 transformed layers */
888             (!tform || num->NV12 == num->possible_overlay_layers) &&
889             /* HDMI cannot display BGR */
890             (num->BGR == 0 || (num->RGB == 0 && !on_tv) || !hwc_dev->flags_rgb_order);
891 }
892 
can_dss_render_layer(omap4_hwc_device_t * hwc_dev,hwc_layer_t * layer)893 static inline int can_dss_render_layer(omap4_hwc_device_t *hwc_dev,
894             hwc_layer_t *layer)
895 {
896     IMG_native_handle_t *handle = (IMG_native_handle_t *)layer->handle;
897 
898     int on_tv = hwc_dev->ext.on_tv;
899     int tform = hwc_dev->ext.current.enabled && (hwc_dev->ext.current.rotation || hwc_dev->ext.current.hflip);
900 
901     return omap4_hwc_is_valid_layer(hwc_dev, layer, handle) &&
902            /* cannot rotate non-NV12 layers on external display */
903            (!tform || is_NV12(handle->iFormat)) &&
904            /* skip non-NV12 layers if also using SGX (if nv12_only flag is set) */
905            (!hwc_dev->flags_nv12_only || (!hwc_dev->use_sgx || is_NV12(handle->iFormat))) &&
906            /* make sure RGB ordering is consistent (if rgb_order flag is set) */
907            (!(hwc_dev->swap_rb ? is_RGB(handle->iFormat) : is_BGR(handle->iFormat)) ||
908             !hwc_dev->flags_rgb_order) &&
909            /* TV can only render RGB */
910            !(on_tv && is_BGR(handle->iFormat));
911 }
912 
display_area(struct dss2_ovl_info * o)913 static inline int display_area(struct dss2_ovl_info *o)
914 {
915     return o->cfg.win.w * o->cfg.win.h;
916 }
917 
omap4_hwc_prepare(struct hwc_composer_device * dev,hwc_layer_list_t * list)918 static int omap4_hwc_prepare(struct hwc_composer_device *dev, hwc_layer_list_t* list)
919 {
920     omap4_hwc_device_t *hwc_dev = (omap4_hwc_device_t *)dev;
921     struct dsscomp_setup_dispc_data *dsscomp = &hwc_dev->dsscomp_data;
922     struct counts num = { .composited_layers = list ? list->numHwLayers : 0 };
923     unsigned int i;
924 
925     pthread_mutex_lock(&hwc_dev->lock);
926     memset(dsscomp, 0x0, sizeof(*dsscomp));
927     dsscomp->sync_id = sync_id++;
928 
929     /* Figure out how many layers we can support via DSS */
930     for (i = 0; list && i < list->numHwLayers; i++) {
931         hwc_layer_t *layer = &list->hwLayers[i];
932         IMG_native_handle_t *handle = (IMG_native_handle_t *)layer->handle;
933 
934         layer->compositionType = HWC_FRAMEBUFFER;
935 
936         if (omap4_hwc_is_valid_layer(hwc_dev, layer, handle)) {
937             num.possible_overlay_layers++;
938 
939             /* NV12 layers can only be rendered on scaling overlays */
940             if (scaled(layer) || is_NV12(handle->iFormat))
941                 num.scaled_layers++;
942 
943             if (is_BGR(handle->iFormat))
944                 num.BGR++;
945             else if (is_RGB(handle->iFormat))
946                 num.RGB++;
947             else if (is_NV12(handle->iFormat))
948                 num.NV12++;
949 
950             if (dockable(layer))
951                 num.dockable++;
952 
953             num.mem += mem1d(handle);
954 
955            /* Check if any of the layers are protected.
956            * if so, disable the SGX force usage
957            */
958             if (hwc_dev->force_sgx && isprotected(layer))
959                 hwc_dev->force_sgx = 0;
960         }
961     }
962 
963     /* phase 3 logic */
964     if (!hwc_dev->force_sgx && can_dss_render_all(hwc_dev, &num)) {
965         /* All layers can be handled by the DSS -- don't use SGX for composition */
966         hwc_dev->use_sgx = 0;
967         hwc_dev->swap_rb = num.BGR != 0;
968     } else {
969         /* Use SGX for composition plus first 3 layers that are DSS renderable */
970         hwc_dev->use_sgx = 1;
971         hwc_dev->swap_rb = is_BGR(hwc_dev->fb_dev->base.format);
972     }
973     if (debug) {
974         LOGD("prepare (%d) - %s (comp=%d, poss=%d/%d scaled, RGB=%d,BGR=%d,NV12=%d) (ext=%s%s%ddeg%s %dex/%dmx (last %dex,%din)\n",
975              dsscomp->sync_id,
976              hwc_dev->use_sgx ? "SGX+OVL" : "all-OVL",
977              num.composited_layers,
978              num.possible_overlay_layers, num.scaled_layers,
979              num.RGB, num.BGR, num.NV12,
980              hwc_dev->ext.on_tv ? "tv+" : "",
981              hwc_dev->ext.current.enabled ? hwc_dev->ext.current.docking ? "dock+" : "mirror+" : "OFF+",
982              hwc_dev->ext.current.rotation * 90,
983              hwc_dev->ext.current.hflip ? "+hflip" : "",
984              hwc_dev->ext_ovls, num.max_hw_overlays, hwc_dev->last_ext_ovls, hwc_dev->last_int_ovls);
985     }
986 
987     /* setup pipes */
988     dsscomp->num_ovls = hwc_dev->use_sgx;
989     int z = 0;
990     int fb_z = -1;
991     int scaled_gfx = 0;
992     int ix_docking = -1;
993 
994     /* set up if DSS layers */
995     unsigned int mem_used = 0;
996     for (i = 0; list && i < list->numHwLayers; i++) {
997         hwc_layer_t *layer = &list->hwLayers[i];
998         IMG_native_handle_t *handle = (IMG_native_handle_t *)layer->handle;
999 
1000         if (!hwc_dev->force_sgx &&
1001             dsscomp->num_ovls < num.max_hw_overlays &&
1002             can_dss_render_layer(hwc_dev, layer) &&
1003             mem_used + mem1d(handle) < MAX_TILER_SLOT &&
1004             /* can't have a transparent overlay in the middle of the framebuffer stack */
1005             !(is_BLENDED(layer->blending) && fb_z >= 0)) {
1006             /* render via DSS overlay */
1007             mem_used += mem1d(handle);
1008             layer->compositionType = HWC_OVERLAY;
1009             hwc_dev->buffers[dsscomp->num_ovls] = handle;
1010 
1011             omap4_hwc_setup_layer(hwc_dev,
1012                                   &dsscomp->ovls[dsscomp->num_ovls],
1013                                   layer,
1014                                   z,
1015                                   handle->iFormat,
1016                                   handle->iWidth,
1017                                   handle->iHeight);
1018 
1019             dsscomp->ovls[dsscomp->num_ovls].cfg.ix = dsscomp->num_ovls;
1020             /* just marking dss layers */
1021             dsscomp->ovls[dsscomp->num_ovls].address = (void *) (dsscomp->num_ovls * 4096 + 0xA0000000);
1022             dsscomp->ovls[dsscomp->num_ovls].uv = (__u32) hwc_dev->buffers[dsscomp->num_ovls];
1023 
1024             /* ensure GFX layer is never scaled */
1025             if (dsscomp->num_ovls == 0) {
1026                 scaled_gfx = scaled(layer) || is_NV12(handle->iFormat);
1027             } else if (scaled_gfx && !scaled(layer) && !is_NV12(handle->iFormat)) {
1028                 /* swap GFX layer with this one */
1029                 dsscomp->ovls[dsscomp->num_ovls].cfg.ix = 0;
1030                 dsscomp->ovls[0].cfg.ix = dsscomp->num_ovls;
1031                 scaled_gfx = 0;
1032             }
1033 
1034             /* remember largest dockable layer */
1035             if (dockable(layer) &&
1036                 (ix_docking < 0 ||
1037                  display_area(dsscomp->ovls + dsscomp->num_ovls) > display_area(dsscomp->ovls + ix_docking)))
1038                 ix_docking = dsscomp->num_ovls;
1039 
1040             dsscomp->num_ovls++;
1041             z++;
1042         } else if (hwc_dev->use_sgx) {
1043             if (fb_z < 0) {
1044                 /* NOTE: we are not handling transparent cutout for now */
1045                 fb_z = z;
1046                 z++;
1047             } else {
1048                 /* move fb z-order up (by lowering dss layers) */
1049                 while (fb_z < z - 1)
1050                     dsscomp->ovls[1 + fb_z++].cfg.zorder--;
1051             }
1052         }
1053     }
1054 
1055     /* clear FB above all opaque layers if rendering via SGX */
1056     if (hwc_dev->use_sgx) {
1057         for (i = 0; list && i < list->numHwLayers; i++) {
1058             hwc_layer_t *layer = &list->hwLayers[i];
1059             IMG_native_handle_t *handle = (IMG_native_handle_t *)layer->handle;
1060             if (layer->compositionType == HWC_FRAMEBUFFER)
1061                 continue;
1062             if ((layer->flags & HWC_SKIP_LAYER) || !layer->handle)
1063                 continue;
1064             if (!is_BLENDED(layer->blending))
1065                 layer->hints |= HWC_HINT_CLEAR_FB;
1066         }
1067     }
1068 
1069     /* if scaling GFX (e.g. only 1 scaled surface) use a VID pipe */
1070     if (scaled_gfx)
1071         dsscomp->ovls[0].cfg.ix = dsscomp->num_ovls;
1072 
1073     /* assign a z-layer for fb */
1074     if (hwc_dev->use_sgx && fb_z < 0) {
1075         fb_z = z;
1076         z++;
1077     }
1078 
1079     if (hwc_dev->use_sgx) {
1080         hwc_dev->buffers[0] = NULL;
1081         omap4_hwc_setup_layer_base(&dsscomp->ovls[0].cfg, fb_z,
1082                                    hwc_dev->fb_dev->base.format,
1083                                    hwc_dev->fb_dev->base.width,
1084                                    hwc_dev->fb_dev->base.height);
1085         dsscomp->ovls[0].cfg.pre_mult_alpha = 1;
1086         dsscomp->ovls[0].uv = (__u32) hwc_dev->buffers[0];
1087     }
1088 
1089     /* mirror layers */
1090     hwc_dev->post2_layers = dsscomp->num_ovls;
1091     if (hwc_dev->ext.current.docking && (ix_docking == -1))
1092         ix_docking = dsscomp->ovls[0].cfg.ix;
1093 
1094     if (hwc_dev->ext.current.enabled && hwc_dev->ext_ovls) {
1095         int ix_back, ix_front, ix;
1096         if (hwc_dev->ext.current.docking) {
1097             /* mirror only 1 external layer */
1098             ix_back = ix_front = ix_docking;
1099         } else {
1100             /* mirror all layers */
1101             ix_back = 0;
1102             ix_front = dsscomp->num_ovls - 1;
1103 
1104             /* reset mode if we are coming from docking */
1105             if (hwc_dev->ext.last.docking) {
1106                 __u32 xres = WIDTH(hwc_dev->ext.mirror_region);
1107                 __u32 yres = HEIGHT(hwc_dev->ext.mirror_region);
1108                 if (hwc_dev->ext.current.rotation & 1)
1109                    swap(xres, yres);
1110                 omap4_hwc_set_best_hdmi_mode(hwc_dev, xres, yres, 1.);
1111                 set_ext_matrix(&hwc_dev->ext, hwc_dev->ext.mirror_region);
1112             }
1113         }
1114 
1115         for (ix = ix_back; hwc_dev->ext.current.enabled && ix >= 0 && ix <= ix_front; ix++) {
1116             struct dss2_ovl_info *o = dsscomp->ovls + dsscomp->num_ovls;
1117             memcpy(o, dsscomp->ovls + ix, sizeof(dsscomp->ovls[ix]));
1118             o->cfg.zorder += hwc_dev->post2_layers;
1119 
1120             /* reserve overlays at end for other display */
1121             o->cfg.ix = MAX_HW_OVERLAYS - 1 - (ix - ix_back);
1122             o->cfg.mgr_ix = 1;
1123             o->ba = ix;
1124 
1125             if (hwc_dev->ext.current.docking) {
1126                 /* full screen video after transformation */
1127                 __u32 xres = o->cfg.crop.w, yres = o->cfg.crop.h;
1128                 if ((hwc_dev->ext.current.rotation + o->cfg.rotation) & 1)
1129                     swap(xres, yres);
1130                 float xpy = (float) o->cfg.win.w / o->cfg.win.h;
1131                 if (o->cfg.rotation & 1)
1132                     xpy = o->cfg.crop.h / xpy / o->cfg.crop.w;
1133                 else
1134                     xpy = o->cfg.crop.h * xpy / o->cfg.crop.w;
1135                 if (hwc_dev->ext.current.rotation & 1)
1136                     xpy = 1. / xpy;
1137 
1138                 /* adjust hdmi mode based on resolution */
1139                 if (xres != hwc_dev->ext.last_xres_used ||
1140                     yres != hwc_dev->ext.last_yres_used ||
1141                     xpy < hwc_dev->ext.last_xpy * (1.f - ASPECT_RATIO_TOLERANCE) ||
1142                     xpy * (1.f - ASPECT_RATIO_TOLERANCE) > hwc_dev->ext.last_xpy) {
1143                     LOGD("set up HDMI for %d*%d\n", xres, yres);
1144                     if (omap4_hwc_set_best_hdmi_mode(hwc_dev, xres, yres, xpy)) {
1145                         o->cfg.enabled = 0;
1146                         hwc_dev->ext.current.enabled = 0;
1147                         continue;
1148                     }
1149                 }
1150 
1151                 struct hwc_rect region = {
1152                     .left = o->cfg.win.x, .top = o->cfg.win.y,
1153                     .right = o->cfg.win.x + o->cfg.win.w,
1154                     .bottom = o->cfg.win.y + o->cfg.win.h
1155                 };
1156                 set_ext_matrix(&hwc_dev->ext, region);
1157             }
1158             omap4_hwc_adjust_ext_layer(&hwc_dev->ext, o);
1159             dsscomp->num_ovls++;
1160             z++;
1161         }
1162     }
1163     hwc_dev->ext.last = hwc_dev->ext.current;
1164 
1165     if (z != dsscomp->num_ovls || dsscomp->num_ovls > MAX_HW_OVERLAYS)
1166         LOGE("**** used %d z-layers for %d overlays\n", z, dsscomp->num_ovls);
1167 
1168     dsscomp->mode = DSSCOMP_SETUP_DISPLAY;
1169     dsscomp->mgrs[0].ix = 0;
1170     dsscomp->mgrs[0].alpha_blending = 1;
1171     dsscomp->mgrs[0].swap_rb = hwc_dev->swap_rb;
1172     dsscomp->num_mgrs = 1;
1173 
1174     if (hwc_dev->ext.current.enabled || hwc_dev->last_ext_ovls) {
1175         dsscomp->mgrs[1] = dsscomp->mgrs[0];
1176         dsscomp->mgrs[1].ix = 1;
1177         dsscomp->num_mgrs++;
1178         hwc_dev->ext_ovls = dsscomp->num_ovls - hwc_dev->post2_layers;
1179     }
1180     pthread_mutex_unlock(&hwc_dev->lock);
1181     return 0;
1182 }
1183 
omap4_hwc_reset_screen(omap4_hwc_device_t * hwc_dev)1184 static void omap4_hwc_reset_screen(omap4_hwc_device_t *hwc_dev)
1185 {
1186     static int first_set = 1;
1187     int ret;
1188 
1189     if (first_set) {
1190         first_set = 0;
1191         struct dsscomp_setup_dispc_data d = {
1192                 .num_mgrs = 1,
1193         };
1194         /* remove bootloader image from the screen as blank/unblank does not change the composition */
1195         ret = ioctl(hwc_dev->dsscomp_fd, DSSCOMP_SETUP_DISPC, &d);
1196         if (ret)
1197             LOGW("failed to remove bootloader image");
1198 
1199         /* blank and unblank fd to make sure display is properly programmed on boot.
1200          * This is needed because the bootloader can not be trusted.
1201          */
1202         ret = ioctl(hwc_dev->fb_fd, FBIOBLANK, FB_BLANK_POWERDOWN);
1203         if (ret)
1204             LOGW("failed to blank display");
1205 
1206         ret = ioctl(hwc_dev->fb_fd, FBIOBLANK, FB_BLANK_UNBLANK);
1207         if (ret)
1208             LOGW("failed to blank display");
1209     }
1210 }
1211 
omap4_hwc_set(struct hwc_composer_device * dev,hwc_display_t dpy,hwc_surface_t sur,hwc_layer_list_t * list)1212 static int omap4_hwc_set(struct hwc_composer_device *dev, hwc_display_t dpy,
1213                hwc_surface_t sur, hwc_layer_list_t* list)
1214 {
1215     omap4_hwc_device_t *hwc_dev = (omap4_hwc_device_t *)dev;
1216     struct dsscomp_setup_dispc_data *dsscomp = &hwc_dev->dsscomp_data;
1217     int err = 0;
1218     unsigned int i;
1219     int invalidate;
1220 
1221     pthread_mutex_lock(&hwc_dev->lock);
1222 
1223     omap4_hwc_reset_screen(hwc_dev);
1224 
1225     invalidate = hwc_dev->ext_ovls_wanted && !hwc_dev->ext_ovls;
1226 
1227     char big_log[1024];
1228     int e = sizeof(big_log);
1229     char *end = big_log + e;
1230     e -= snprintf(end - e, e, "set H{");
1231     for (i = 0; list && i < list->numHwLayers; i++) {
1232         if (i)
1233             e -= snprintf(end - e, e, " ");
1234         hwc_layer_t *layer = &list->hwLayers[i];
1235         IMG_native_handle_t *handle = (IMG_native_handle_t *)layer->handle;
1236         e -= snprintf(end - e, e, "%p:%s,", handle, layer->compositionType == HWC_OVERLAY ? "DSS" : "SGX");
1237         if ((layer->flags & HWC_SKIP_LAYER) || !handle) {
1238             e -= snprintf(end - e, e, "SKIP");
1239             continue;
1240         }
1241         if (layer->flags & HWC_HINT_CLEAR_FB)
1242             e -= snprintf(end - e, e, "CLR,");
1243 #define FMT(f) ((f) == HAL_PIXEL_FORMAT_TI_NV12 ? "NV12" : \
1244                 (f) == HAL_PIXEL_FORMAT_BGRX_8888 ? "xRGB32" : \
1245                 (f) == HAL_PIXEL_FORMAT_RGBX_8888 ? "xBGR32" : \
1246                 (f) == HAL_PIXEL_FORMAT_BGRA_8888 ? "ARGB32" : \
1247                 (f) == HAL_PIXEL_FORMAT_RGBA_8888 ? "ABGR32" : \
1248                 (f) == HAL_PIXEL_FORMAT_RGB_565 ? "RGB565" : "??")
1249         e -= snprintf(end - e, e, "%d*%d(%s)", handle->iWidth, handle->iHeight, FMT(handle->iFormat));
1250         if (layer->transform)
1251             e -= snprintf(end - e, e, "~%d", layer->transform);
1252 #undef FMT
1253     }
1254     e -= snprintf(end - e, e, "} D{");
1255     for (i = 0; i < dsscomp->num_ovls; i++) {
1256         if (i)
1257             e -= snprintf(end - e, e, " ");
1258         e -= snprintf(end - e, e, "%d=", dsscomp->ovls[i].cfg.ix);
1259 #define FMT(f) ((f) == OMAP_DSS_COLOR_NV12 ? "NV12" : \
1260                 (f) == OMAP_DSS_COLOR_RGB24U ? "xRGB32" : \
1261                 (f) == OMAP_DSS_COLOR_ARGB32 ? "ARGB32" : \
1262                 (f) == OMAP_DSS_COLOR_RGB16 ? "RGB565" : "??")
1263         if (dsscomp->ovls[i].cfg.enabled)
1264             e -= snprintf(end - e, e, "%08x:%d*%d,%s",
1265                           dsscomp->ovls[i].ba,
1266                           dsscomp->ovls[i].cfg.width,
1267                           dsscomp->ovls[i].cfg.height,
1268                           FMT(dsscomp->ovls[i].cfg.color_mode));
1269 #undef FMT
1270         else
1271             e -= snprintf(end - e, e, "-");
1272     }
1273     e -= snprintf(end - e, e, "} L{");
1274     for (i = 0; i < hwc_dev->post2_layers; i++) {
1275         if (i)
1276             e -= snprintf(end - e, e, " ");
1277         e -= snprintf(end - e, e, "%p", hwc_dev->buffers[i]);
1278     }
1279     e -= snprintf(end - e, e, "}%s\n", hwc_dev->use_sgx ? " swap" : "");
1280     if (debug) {
1281         LOGD("%s", big_log);
1282     }
1283 
1284     // LOGD("set %d layers (sgx=%d)\n", dsscomp->num_ovls, hwc_dev->use_sgx);
1285 
1286     if (dpy && sur) {
1287         // list can be NULL which means hwc is temporarily disabled.
1288         // however, if dpy and sur are null it means we're turning the
1289         // screen off. no shall not call eglSwapBuffers() in that case.
1290 
1291         if (hwc_dev->use_sgx) {
1292             if (!eglSwapBuffers((EGLDisplay)dpy, (EGLSurface)sur)) {
1293                 LOGE("eglSwapBuffers error");
1294                 err = HWC_EGL_ERROR;
1295                 goto err_out;
1296             }
1297         }
1298 
1299         //dump_dsscomp(dsscomp);
1300 
1301         // signal the event thread that a post has happened
1302         write(hwc_dev->pipe_fds[1], "s", 1);
1303         if (hwc_dev->force_sgx > 0)
1304             hwc_dev->force_sgx--;
1305 
1306         err = hwc_dev->fb_dev->Post2((framebuffer_device_t *)hwc_dev->fb_dev,
1307                                  hwc_dev->buffers,
1308                                  hwc_dev->post2_layers,
1309                                  dsscomp, sizeof(*dsscomp));
1310 
1311         if (!hwc_dev->use_sgx) {
1312             __u32 crt = 0;
1313             int err2 = ioctl(hwc_dev->fb_fd, FBIO_WAITFORVSYNC, &crt);
1314             if (err2) {
1315                 LOGE("failed to wait for vsync (%d)", errno);
1316                 err = err ? : -errno;
1317             }
1318         }
1319     }
1320     hwc_dev->last_ext_ovls = hwc_dev->ext_ovls;
1321     hwc_dev->last_int_ovls = hwc_dev->post2_layers;
1322     if (err)
1323         LOGE("Post2 error");
1324 
1325 err_out:
1326     pthread_mutex_unlock(&hwc_dev->lock);
1327 
1328     if (invalidate && hwc_dev->procs && hwc_dev->procs->invalidate)
1329         hwc_dev->procs->invalidate(hwc_dev->procs);
1330 
1331     return err;
1332 }
1333 
dump_printf(char * buff,int buff_len,int len,const char * fmt,...)1334 static int dump_printf(char *buff, int buff_len, int len, const char *fmt, ...)
1335 {
1336     va_list ap;
1337 
1338     int print_len;
1339 
1340     va_start(ap, fmt);
1341 
1342     print_len = vsnprintf(buff + len, buff_len - len, fmt, ap);
1343 
1344     va_end(ap);
1345 
1346     return len + print_len;
1347 }
1348 
omap4_hwc_dump(struct hwc_composer_device * dev,char * buff,int buff_len)1349 static void omap4_hwc_dump(struct hwc_composer_device *dev, char *buff, int buff_len)
1350 {
1351     omap4_hwc_device_t *hwc_dev = (omap4_hwc_device_t *)dev;
1352     struct dsscomp_setup_dispc_data *dsscomp = &hwc_dev->dsscomp_data;
1353     int len = 0;
1354     int i;
1355 
1356     len = dump_printf(buff, buff_len, len, "omap4_hwc %d:\n", dsscomp->num_ovls);
1357     len = dump_printf(buff, buff_len, len, "  idle timeout: %dms\n", hwc_dev->idle);
1358 
1359     for (i = 0; i < dsscomp->num_ovls; i++) {
1360         struct dss2_ovl_cfg *cfg = &dsscomp->ovls[i].cfg;
1361 
1362         len = dump_printf(buff, buff_len, len, "  layer %d:\n", i);
1363         len = dump_printf(buff, buff_len, len, "     enabled: %s\n",
1364                           cfg->enabled ? "true" : "false");
1365         len = dump_printf(buff, buff_len, len, "     buff: %p %dx%d stride: %d\n",
1366                           hwc_dev->buffers[i], cfg->width, cfg->height, cfg->stride);
1367         len = dump_printf(buff, buff_len, len, "     src: (%d,%d) %dx%d\n",
1368                           cfg->crop.x, cfg->crop.y, cfg->crop.w, cfg->crop.h);
1369         len = dump_printf(buff, buff_len, len, "     dst: (%d,%d) %dx%d\n",
1370                           cfg->win.x, cfg->win.y, cfg->win.w, cfg->win.h);
1371         len = dump_printf(buff, buff_len, len, "     ix: %d\n", cfg->ix);
1372         len = dump_printf(buff, buff_len, len, "     zorder: %d\n\n", cfg->zorder);
1373     }
1374 }
1375 
1376 
omap4_hwc_device_close(hw_device_t * device)1377 static int omap4_hwc_device_close(hw_device_t* device)
1378 {
1379     omap4_hwc_device_t *hwc_dev = (omap4_hwc_device_t *) device;;
1380 
1381     if (hwc_dev) {
1382         if (hwc_dev->dsscomp_fd >= 0)
1383             close(hwc_dev->dsscomp_fd);
1384         if (hwc_dev->hdmi_fb_fd >= 0)
1385             close(hwc_dev->hdmi_fb_fd);
1386         if (hwc_dev->fb_fd >= 0)
1387             close(hwc_dev->fb_fd);
1388         /* pthread will get killed when parent process exits */
1389         pthread_mutex_destroy(&hwc_dev->lock);
1390         free(hwc_dev);
1391     }
1392 
1393     return 0;
1394 }
1395 
omap4_hwc_open_fb_hal(IMG_framebuffer_device_public_t ** fb_dev)1396 static int omap4_hwc_open_fb_hal(IMG_framebuffer_device_public_t **fb_dev)
1397 {
1398     IMG_gralloc_module_public_t *psGrallocModule;
1399     int err;
1400 
1401     err = hw_get_module(GRALLOC_HARDWARE_MODULE_ID,
1402                         (const hw_module_t**)&psGrallocModule);
1403     if(err)
1404         goto err_out;
1405 
1406     if(strcmp(psGrallocModule->base.common.author,
1407               "Imagination Technologies"))
1408     {
1409         err = -EINVAL;
1410         goto err_out;
1411     }
1412 
1413     *fb_dev = psGrallocModule->psFrameBufferDevice;
1414 
1415     return 0;
1416 
1417 err_out:
1418     LOGE("Composer HAL failed to load compatible Graphics HAL");
1419     return err;
1420 }
1421 
handle_hotplug(omap4_hwc_device_t * hwc_dev,int state)1422 static void handle_hotplug(omap4_hwc_device_t *hwc_dev, int state)
1423 {
1424     omap4_hwc_ext_t *ext = &hwc_dev->ext;
1425 
1426     pthread_mutex_lock(&hwc_dev->lock);
1427     ext->dock.enabled = ext->mirror.enabled = 0;
1428     if (state) {
1429         /* check whether we can clone and/or dock */
1430         char value[PROPERTY_VALUE_MAX];
1431         property_get("persist.hwc.docking.enabled", value, "1");
1432         ext->dock.enabled = atoi(value) > 0;
1433         property_get("persist.hwc.mirroring.enabled", value, "1");
1434         ext->mirror.enabled = atoi(value) > 0;
1435         property_get("persist.hwc.avoid_mode_change", value, "1");
1436         ext->avoid_mode_change = atoi(value) > 0;
1437 
1438         /* get cloning transformation */
1439         property_get("persist.hwc.docking.transform", value, "0");
1440         ext->dock.rotation = atoi(value) & EXT_ROTATION;
1441         ext->dock.hflip = (atoi(value) & EXT_HFLIP) > 0;
1442         ext->dock.docking = 1;
1443         property_get("persist.hwc.mirroring.transform", value, hwc_dev->fb_dev->base.height > hwc_dev->fb_dev->base.width ? "3" : "0");
1444         ext->mirror.rotation = atoi(value) & EXT_ROTATION;
1445         ext->mirror.hflip = (atoi(value) & EXT_HFLIP) > 0;
1446         ext->mirror.docking = 0;
1447 
1448         /* select best mode for mirroring */
1449         if (ext->mirror.enabled) {
1450             __u32 xres = WIDTH(ext->mirror_region);
1451             __u32 yres = HEIGHT(ext->mirror_region);
1452             if (ext->mirror.rotation & 1)
1453                swap(xres, yres);
1454 	    ext->mirror_mode = 0;
1455             int res = omap4_hwc_set_best_hdmi_mode(hwc_dev, xres, yres, 1.);
1456             if (!res) {
1457                 ext->mirror_mode = ext->last_mode;
1458                 ioctl(hwc_dev->hdmi_fb_fd, FBIOBLANK, FB_BLANK_UNBLANK);
1459             } else
1460                 ext->mirror.enabled = 0;
1461         }
1462     } else {
1463         ext->last_mode = 0;
1464     }
1465     omap4_hwc_create_ext_matrix(ext);
1466     LOGI("external display changed (state=%d, mirror={%s tform=%ddeg%s}, dock={%s tform=%ddeg%s}, tv=%d", state,
1467          ext->mirror.enabled ? "enabled" : "disabled",
1468          ext->mirror.rotation * 90,
1469          ext->mirror.hflip ? "+hflip" : "",
1470          ext->dock.enabled ? "enabled" : "disabled",
1471          ext->dock.rotation * 90,
1472          ext->dock.hflip ? "+hflip" : "",
1473          ext->on_tv);
1474 
1475     pthread_mutex_unlock(&hwc_dev->lock);
1476 
1477     if (hwc_dev->procs && hwc_dev->procs->invalidate)
1478             hwc_dev->procs->invalidate(hwc_dev->procs);
1479 }
1480 
handle_uevents(omap4_hwc_device_t * hwc_dev,const char * s)1481 static void handle_uevents(omap4_hwc_device_t *hwc_dev, const char *s)
1482 {
1483     if (strcmp(s, "change@/devices/virtual/switch/hdmi"))
1484         return;
1485 
1486     s += strlen(s) + 1;
1487 
1488     while(*s) {
1489         if (!strncmp(s, "SWITCH_STATE=", strlen("SWITCH_STATE="))) {
1490             int state = atoi(s + strlen("SWITCH_STATE="));
1491             handle_hotplug(hwc_dev, state);
1492         }
1493 
1494         s += strlen(s) + 1;
1495     }
1496 }
1497 
omap4_hwc_hdmi_thread(void * data)1498 static void *omap4_hwc_hdmi_thread(void *data)
1499 {
1500     omap4_hwc_device_t *hwc_dev = data;
1501     static char uevent_desc[4096];
1502     struct pollfd fds[2];
1503     int prev_force_sgx = 0;
1504     int timeout;
1505     int err;
1506 
1507     uevent_init();
1508 
1509     fds[0].fd = uevent_get_fd();
1510     fds[0].events = POLLIN;
1511     fds[1].fd = hwc_dev->pipe_fds[0];
1512     fds[1].events = POLLIN;
1513 
1514     timeout = hwc_dev->idle ? hwc_dev->idle : -1;
1515 
1516     memset(uevent_desc, 0, sizeof(uevent_desc));
1517 
1518     do {
1519         err = poll(fds, hwc_dev->idle ? 2 : 1, timeout);
1520 
1521         if (err == 0) {
1522             if (hwc_dev->idle) {
1523                 pthread_mutex_lock(&hwc_dev->lock);
1524                 prev_force_sgx = hwc_dev->force_sgx;
1525                 hwc_dev->force_sgx = 2;
1526                 pthread_mutex_unlock(&hwc_dev->lock);
1527 
1528                 if (!prev_force_sgx && hwc_dev->procs && hwc_dev->procs->invalidate) {
1529                     hwc_dev->procs->invalidate(hwc_dev->procs);
1530                     timeout = -1;
1531                 }
1532 
1533                 continue;
1534             }
1535         }
1536 
1537         if (err == -1) {
1538             if (errno != EINTR)
1539                 LOGE("event error: %m");
1540             continue;
1541         }
1542 
1543         if (hwc_dev->idle && fds[1].revents & POLLIN) {
1544             char c;
1545             read(hwc_dev->pipe_fds[0], &c, 1);
1546             if (!hwc_dev->force_sgx)
1547                 timeout = hwc_dev->idle ? hwc_dev->idle : -1;
1548         }
1549 
1550         if (fds[0].revents & POLLIN) {
1551             /* keep last 2 zeroes to ensure double 0 termination */
1552             uevent_next_event(uevent_desc, sizeof(uevent_desc) - 2);
1553             handle_uevents(hwc_dev, uevent_desc);
1554         }
1555     } while (1);
1556 
1557     return NULL;
1558 }
1559 
omap4_hwc_registerProcs(struct hwc_composer_device * dev,hwc_procs_t const * procs)1560 static void omap4_hwc_registerProcs(struct hwc_composer_device* dev,
1561                                     hwc_procs_t const* procs)
1562 {
1563         omap4_hwc_device_t *hwc_dev = (omap4_hwc_device_t *) dev;
1564 
1565         hwc_dev->procs = (typeof(hwc_dev->procs)) procs;
1566 }
1567 
omap4_hwc_device_open(const hw_module_t * module,const char * name,hw_device_t ** device)1568 static int omap4_hwc_device_open(const hw_module_t* module, const char* name,
1569                 hw_device_t** device)
1570 {
1571     omap4_hwc_module_t *hwc_mod = (omap4_hwc_module_t *)module;
1572     omap4_hwc_device_t *hwc_dev;
1573     int err = 0;
1574 
1575     if (strcmp(name, HWC_HARDWARE_COMPOSER)) {
1576         return -EINVAL;
1577     }
1578 
1579     if (!hwc_mod->fb_dev) {
1580         err = omap4_hwc_open_fb_hal(&hwc_mod->fb_dev);
1581         if (err)
1582             return err;
1583 
1584         if (!hwc_mod->fb_dev) {
1585             LOGE("Framebuffer HAL not opened before HWC");
1586             return -EFAULT;
1587         }
1588         hwc_mod->fb_dev->bBypassPost = 1;
1589     }
1590 
1591     hwc_dev = (omap4_hwc_device_t *)malloc(sizeof(*hwc_dev));
1592     if (hwc_dev == NULL)
1593         return -ENOMEM;
1594 
1595     memset(hwc_dev, 0, sizeof(*hwc_dev));
1596 
1597     hwc_dev->base.common.tag = HARDWARE_DEVICE_TAG;
1598     hwc_dev->base.common.version = HWC_API_VERSION;
1599     hwc_dev->base.common.module = (hw_module_t *)module;
1600     hwc_dev->base.common.close = omap4_hwc_device_close;
1601     hwc_dev->base.prepare = omap4_hwc_prepare;
1602     hwc_dev->base.set = omap4_hwc_set;
1603     hwc_dev->base.dump = omap4_hwc_dump;
1604     hwc_dev->base.registerProcs = omap4_hwc_registerProcs;
1605     hwc_dev->fb_dev = hwc_mod->fb_dev;
1606     *device = &hwc_dev->base.common;
1607 
1608     hwc_dev->dsscomp_fd = open("/dev/dsscomp", O_RDWR);
1609     if (hwc_dev->dsscomp_fd < 0) {
1610         LOGE("failed to open dsscomp (%d)", errno);
1611         err = -errno;
1612         goto done;
1613     }
1614 
1615     hwc_dev->hdmi_fb_fd = open("/dev/graphics/fb1", O_RDWR);
1616     if (hwc_dev->hdmi_fb_fd < 0) {
1617         LOGE("failed to open hdmi fb (%d)", errno);
1618         err = -errno;
1619         goto done;
1620     }
1621 
1622     hwc_dev->fb_fd = open("/dev/graphics/fb0", O_RDWR);
1623     if (hwc_dev->fb_fd < 0) {
1624         LOGE("failed to open fb (%d)", errno);
1625         err = -errno;
1626         goto done;
1627     }
1628 
1629     hwc_dev->buffers = malloc(sizeof(buffer_handle_t) * MAX_HW_OVERLAYS);
1630     if (!hwc_dev->buffers) {
1631         err = -ENOMEM;
1632         goto done;
1633     }
1634 
1635     int ret = ioctl(hwc_dev->dsscomp_fd, DSSCOMP_QUERY_DISPLAY, &hwc_dev->fb_dis);
1636     if (ret) {
1637         LOGE("failed to get display info (%d): %m", errno);
1638         err = -errno;
1639         goto done;
1640     }
1641 
1642     if (pipe(hwc_dev->pipe_fds) == -1) {
1643             LOGE("failed to event pipe (%d): %m", errno);
1644             err = -errno;
1645             goto done;
1646     }
1647 
1648     if (pthread_mutex_init(&hwc_dev->lock, NULL)) {
1649             LOGE("failed to create mutex (%d): %m", errno);
1650             err = -errno;
1651             goto done;
1652     }
1653     if (pthread_create(&hwc_dev->hdmi_thread, NULL, omap4_hwc_hdmi_thread, hwc_dev))
1654     {
1655             LOGE("failed to create HDMI listening thread (%d): %m", errno);
1656             err = -errno;
1657             goto done;
1658     }
1659 
1660     /* get debug properties */
1661 
1662     /* see if hwc is enabled at all */
1663     char value[PROPERTY_VALUE_MAX];
1664     property_get("debug.hwc.rgb_order", value, "1");
1665     hwc_dev->flags_rgb_order = atoi(value);
1666     property_get("debug.hwc.nv12_only", value, "0");
1667     hwc_dev->flags_nv12_only = atoi(value);
1668     property_get("debug.hwc.idle", value, "250");
1669     hwc_dev->idle = atoi(value);
1670 
1671     /* get the board specific clone properties */
1672     /* 0:0:1280:720 */
1673     if (property_get("persist.hwc.mirroring.region", value, "") <= 0 ||
1674         sscanf(value, "%d:%d:%d:%d",
1675                &hwc_dev->ext.mirror_region.left, &hwc_dev->ext.mirror_region.top,
1676                &hwc_dev->ext.mirror_region.right, &hwc_dev->ext.mirror_region.bottom) != 4 ||
1677         hwc_dev->ext.mirror_region.left >= hwc_dev->ext.mirror_region.right ||
1678         hwc_dev->ext.mirror_region.top >= hwc_dev->ext.mirror_region.bottom) {
1679         struct hwc_rect fb_region = { .right = hwc_dev->fb_dev->base.width, .bottom = hwc_dev->fb_dev->base.height };
1680         hwc_dev->ext.mirror_region = fb_region;
1681     }
1682     LOGI("clone region is set to (%d,%d) to (%d,%d)",
1683          hwc_dev->ext.mirror_region.left, hwc_dev->ext.mirror_region.top,
1684          hwc_dev->ext.mirror_region.right, hwc_dev->ext.mirror_region.bottom);
1685 
1686     /* read switch state */
1687     int sw_fd = open("/sys/class/switch/hdmi/state", O_RDONLY);
1688     int hpd = 0;
1689     if (sw_fd >= 0) {
1690         char value;
1691         if (read(sw_fd, &value, 1) == 1)
1692             hpd = value == '1';
1693         close(sw_fd);
1694     }
1695     handle_hotplug(hwc_dev, hpd);
1696 
1697     LOGE("omap4_hwc_device_open(rgb_order=%d nv12_only=%d)",
1698         hwc_dev->flags_rgb_order, hwc_dev->flags_nv12_only);
1699 
1700 done:
1701     if (err && hwc_dev) {
1702         if (hwc_dev->dsscomp_fd >= 0)
1703             close(hwc_dev->dsscomp_fd);
1704         if (hwc_dev->hdmi_fb_fd >= 0)
1705             close(hwc_dev->hdmi_fb_fd);
1706         if (hwc_dev->fb_fd >= 0)
1707             close(hwc_dev->fb_fd);
1708         pthread_mutex_destroy(&hwc_dev->lock);
1709         free(hwc_dev->buffers);
1710         free(hwc_dev);
1711     }
1712 
1713     return err;
1714 }
1715 
1716 static struct hw_module_methods_t omap4_hwc_module_methods = {
1717     .open = omap4_hwc_device_open,
1718 };
1719 
1720 omap4_hwc_module_t HAL_MODULE_INFO_SYM = {
1721     .base = {
1722         .common = {
1723             .tag =                  HARDWARE_MODULE_TAG,
1724             .version_major =        1,
1725             .version_minor =        0,
1726             .id =                   HWC_HARDWARE_MODULE_ID,
1727             .name =                 "OMAP 44xx Hardware Composer HAL",
1728             .author =               "Texas Instruments",
1729             .methods =              &omap4_hwc_module_methods,
1730         },
1731     },
1732 };
1733