345   SUnit *PredSU = PredEdge->getSUnit();  in ReleasePred()  local
348   if (PredSU->NumSuccsLeft == 0) {  in ReleasePred()
350     PredSU->dump(this);  in ReleasePred()
355   --PredSU->NumSuccsLeft;  in ReleasePred()
360     PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());  in ReleasePred()
365   if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {  in ReleasePred()
366     PredSU->isAvailable = true;  in ReleasePred()
368     unsigned Height = PredSU->getHeight();  in ReleasePred()
372     if (isReady(PredSU)) {  in ReleasePred()
373       AvailableQueue->push(PredSU);  in ReleasePred()
377     else if (!PredSU->isPending) {  in ReleasePred()
378       PredSU->isPending = true;  in ReleasePred()
379       PendingQueue.push_back(PredSU);  in ReleasePred()
767   SUnit *PredSU = PredEdge->getSUnit();  in CapturePred()  local
768   if (PredSU->isAvailable) {  in CapturePred()
769     PredSU->isAvailable = false;  in CapturePred()
770     if (!PredSU->isPending)  in CapturePred()
771       AvailableQueue->remove(PredSU);  in CapturePred()
774   assert(PredSU->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!");  in CapturePred()
775   ++PredSU->NumSuccsLeft;  in CapturePred()
1813     SUnit *PredSU = I->getSUnit();  in CalcNodeSethiUllmanNumber()  local
1814     unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers);  in CalcNodeSethiUllmanNumber()
1914     SUnit *PredSU = I->getSUnit();  in HighRegPressure()  local
1917     if (PredSU->NumRegDefsLeft == 0) {  in HighRegPressure()
1920     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in HighRegPressure()
1964     SUnit *PredSU = I->getSUnit();  in RegPressureDiff()  local
1967     if (PredSU->NumRegDefsLeft == 0) {  in RegPressureDiff()
1968       if (PredSU->getNode()->isMachineOpcode())  in RegPressureDiff()
1972     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in RegPressureDiff()
2008     SUnit *PredSU = I->getSUnit();  in scheduledNode()  local
2011     if (PredSU->NumRegDefsLeft == 0) {  in scheduledNode()
2029     --PredSU->NumRegDefsLeft;  in scheduledNode()
2030     unsigned SkipRegDefs = PredSU->NumRegDefsLeft;  in scheduledNode()
2031     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in scheduledNode()
2090     SUnit *PredSU = I->getSUnit();  in unscheduledNode()  local
2093     if (PredSU->NumSuccsLeft != PredSU->Succs.size())  in unscheduledNode()
2095     const SDNode *PN = PredSU->getNode();  in unscheduledNode()
2189     const SUnit *PredSU = I->getSUnit();  in hasOnlyLiveInOpers()  local
2190     if (PredSU->getNode() &&  in hasOnlyLiveInOpers()
2191         PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {  in hasOnlyLiveInOpers()
2193         cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();  in hasOnlyLiveInOpers()
2263     SUnit *PredSU = I->getSUnit();  in resetVRegCycle()  local
2264     if (PredSU->isVRegCycle) {  in resetVRegCycle()
2265       assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&  in resetVRegCycle()
2796     SUnit *PredSU = 0;  in PrescheduleNodesWithMultipleUses()  local
2800         PredSU = II->getSUnit();  in PrescheduleNodesWithMultipleUses()
2803     assert(PredSU);  in PrescheduleNodesWithMultipleUses()
2807     if (PredSU->hasPhysRegDefs)  in PrescheduleNodesWithMultipleUses()
2810     if (PredSU->NumSuccs == 1)  in PrescheduleNodesWithMultipleUses()
2821     for (SUnit::const_succ_iterator II = PredSU->Succs.begin(),  in PrescheduleNodesWithMultipleUses()
2822          EE = PredSU->Succs.end(); II != EE; ++II) {  in PrescheduleNodesWithMultipleUses()
2841                  << " next to PredSU #" << PredSU->NodeNum  in PrescheduleNodesWithMultipleUses()
2843     for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {  in PrescheduleNodesWithMultipleUses()
2844       SDep Edge = PredSU->Succs[i];  in PrescheduleNodesWithMultipleUses()
2848         Edge.setSUnit(PredSU);  in PrescheduleNodesWithMultipleUses()