388   unsigned DstReg = MI.getOperand(OpIdx++).getReg();  in ExpandVLD()  local
390   GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);  in ExpandVLD()
428   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandVLD()
515   unsigned DstReg = 0;  in ExpandLaneOp()  local
519     DstReg = MI.getOperand(OpIdx++).getReg();  in ExpandLaneOp()
520     GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);  in ExpandLaneOp()
569     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandLaneOp()
616   unsigned DstReg = MI.getOperand(0).getReg();  in ExpandMOV32BitImm()  local
625     LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);  in ExpandMOV32BitImm()
627       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
628       .addReg(DstReg);  in ExpandMOV32BitImm()
655   LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);  in ExpandMOV32BitImm()
657     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMOV32BitImm()
658     .addReg(DstReg);  in ExpandMOV32BitImm()
866       unsigned DstReg = MI.getOperand(0).getReg();  in ExpandMI()  local
870                                TII->get(NewLdOpc), DstReg)  in ExpandMI()
875         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
876         .addReg(DstReg)  in ExpandMI()
890       unsigned DstReg = MI.getOperand(0).getReg();  in ExpandMI()  local
907                                          TII->get(LO16Opc), DstReg)  in ExpandMI()
911                                          TII->get(HI16Opc), DstReg)  in ExpandMI()
912         .addReg(DstReg)  in ExpandMI()
923         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))  in ExpandMI()
924         .addReg(DstReg).addImm(LabelId);  in ExpandMI()
950       unsigned DstReg = MI.getOperand(OpIdx++).getReg();  in ExpandMI()  local
960       unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);  in ExpandMI()
961       unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);  in ExpandMI()
966       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));  in ExpandMI()