94                   int Offset, unsigned Base, bool BaseKill, int Opcode,
107                         int Opcode,
114                       int Opcode, unsigned Size,
137 static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {  in getLoadStoreMultipleOpcode()  argument
138   switch (Opcode) {  in getLoadStoreMultipleOpcode()
208 AMSubMode getLoadStoreMultipleSubMode(int Opcode) {  in getLoadStoreMultipleSubMode()  argument
209   switch (Opcode) {  in getLoadStoreMultipleSubMode()
285                           int Opcode, ARMCC::CondCodes Pred,  in MergeOps()  argument
296   bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);  in MergeOps()
308     if (!getLoadStoreMultipleOpcode(Opcode, Mode)) return false;  in MergeOps()
317     if (isi32Load(Opcode))  in MergeOps()
345   bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS ||  in MergeOps()
346                 Opcode == ARM::VLDRD);  in MergeOps()
347   Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);  in MergeOps()
348   if (!Opcode) return false;  in MergeOps()
349   MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))  in MergeOps()
370                                      int Opcode,  in MergeOpsUpdate()  argument
415   if (!MergeOps(MBB, Loc, Offset, Base, BaseKill, Opcode,  in MergeOpsUpdate()
447                           unsigned Base, int Opcode, unsigned Size,  in MergeLDR_STR()  argument
451   bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);  in MergeLDR_STR()
466   switch (Opcode) {  in MergeLDR_STR()
501                      Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges);  in MergeLDR_STR()
502       MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,  in MergeLDR_STR()
513                  Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);  in MergeLDR_STR()
722   int Opcode = MI->getOpcode();  in MergeBaseUpdateLSMultiple()  local
732   ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(Opcode);  in MergeBaseUpdateLSMultiple()
778   unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);  in MergeBaseUpdateLSMultiple()
856   int Opcode = MI->getOpcode();  in MergeBaseUpdateLoadStore()  local
858   bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||  in MergeBaseUpdateLoadStore()
859                 Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);  in MergeBaseUpdateLoadStore()
860   bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12);  in MergeBaseUpdateLoadStore()
861   if (isi32Load(Opcode) || isi32Store(Opcode))  in MergeBaseUpdateLoadStore()
867   bool isLd = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD;  in MergeBaseUpdateLoadStore()
895       NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub);  in MergeBaseUpdateLoadStore()
914       NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub);  in MergeBaseUpdateLoadStore()
1014   int Opcode = MI->getOpcode();  in isMemoryOp()  local
1015   switch (Opcode) {  in isMemoryOp()
1051   int Opcode = MI->getOpcode();  in getMemoryOpOffset()  local
1052   bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;  in getMemoryOpOffset()
1056   if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||  in getMemoryOpOffset()
1057       Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||  in getMemoryOpOffset()
1058       Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||  in getMemoryOpOffset()
1059       Opcode == ARM::LDRi12   || Opcode == ARM::STRi12)  in getMemoryOpOffset()
1101   unsigned Opcode = MI->getOpcode();  in FixInvalidRegPairOp()  local
1102   if (Opcode == ARM::LDRD || Opcode == ARM::STRD ||  in FixInvalidRegPairOp()
1103       Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) {  in FixInvalidRegPairOp()
1118     bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;  in FixInvalidRegPairOp()
1119     bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;  in FixInvalidRegPairOp()
1247       int Opcode = MBBI->getOpcode();  in LoadStoreMultipleOpti()  local
1265       Clobber = (isi32Load(Opcode) && Base == MBBI->getOperand(0).getReg());  in LoadStoreMultipleOpti()
1269         CurrOpc  = Opcode;  in LoadStoreMultipleOpti()
1282         if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {  in LoadStoreMultipleOpti()
1403     unsigned Opcode = PrevMI->getOpcode();  in MergeReturnIntoLDM()  local
1404     if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD ||  in MergeReturnIntoLDM()
1405         Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD ||  in MergeReturnIntoLDM()
1406         Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {  in MergeReturnIntoLDM()
1411       assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) ||  in MergeReturnIntoLDM()
1412               Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!");  in MergeReturnIntoLDM()
1577   unsigned Opcode = Op0->getOpcode();  in CanFormLdStDWord()  local
1578   if (Opcode == ARM::LDRi12)  in CanFormLdStDWord()
1580   else if (Opcode == ARM::STRi12)  in CanFormLdStDWord()
1582   else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) {  in CanFormLdStDWord()
1586   } else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) {  in CanFormLdStDWord()