95                   ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
109                         unsigned PredReg,
115                       ARMCC::CondCodes Pred, unsigned PredReg,
286                           unsigned PredReg, unsigned Scratch, DebugLoc dl,  in MergeOps()  argument
340       .addImm(Pred).addReg(PredReg).addReg(0);  in MergeOps()
351     .addImm(Pred).addReg(PredReg);  in MergeOps()
371                                      ARMCC::CondCodes Pred, unsigned PredReg,  in MergeOpsUpdate()  argument
416                 Pred, PredReg, Scratch, dl, Regs, ImpDefs))  in MergeOpsUpdate()
448                           ARMCC::CondCodes Pred, unsigned PredReg,  in MergeLDR_STR()  argument
501                      Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges);  in MergeLDR_STR()
502       MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,  in MergeLDR_STR()
513                  Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);  in MergeLDR_STR()
533                                 ARMCC::CondCodes Pred, unsigned PredReg) {  in isMatchingDecrement()  argument
558         MyPredReg == PredReg))  in isMatchingDecrement()
566                                 ARMCC::CondCodes Pred, unsigned PredReg) {  in isMatchingIncrement()  argument
591         MyPredReg == PredReg))  in isMatchingIncrement()
720   unsigned PredReg = 0;  in MergeBaseUpdateLSMultiple()  local
721   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);  in MergeBaseUpdateLSMultiple()
741         isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {  in MergeBaseUpdateLSMultiple()
745                isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {  in MergeBaseUpdateLSMultiple()
760         isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {  in MergeBaseUpdateLSMultiple()
763                isMatchingDecrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {  in MergeBaseUpdateLSMultiple()
782     .addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLSMultiple()
873   unsigned PredReg = 0;  in MergeBaseUpdateLoadStore()  local
874   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);  in MergeBaseUpdateLoadStore()
887     if (isMatchingDecrement(PrevMBBI, Base, Bytes, Limit, Pred, PredReg)) {  in MergeBaseUpdateLoadStore()
891                isMatchingIncrement(PrevMBBI, Base, Bytes, Limit,Pred,PredReg)) {  in MergeBaseUpdateLoadStore()
907         isMatchingDecrement(NextMBBI, Base, Bytes, Limit, Pred, PredReg)) {  in MergeBaseUpdateLoadStore()
910     } else if (isMatchingIncrement(NextMBBI, Base, Bytes, Limit,Pred,PredReg)) {  in MergeBaseUpdateLoadStore()
935       .addImm(Pred).addReg(PredReg)  in MergeBaseUpdateLoadStore()
945           .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLoadStore()
950           .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLoadStore()
957         .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLoadStore()
969         .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLoadStore()
975         .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);  in MergeBaseUpdateLoadStore()
1081                           ARMCC::CondCodes Pred, unsigned PredReg,  in InsertLDR_STR()  argument
1088     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1094     MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in InsertLDR_STR()
1131     unsigned PredReg = 0;  in FixInvalidRegPairOp()  local
1132     ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);  in FixInvalidRegPairOp()
1143           .addImm(Pred).addReg(PredReg)  in FixInvalidRegPairOp()
1150           .addImm(Pred).addReg(PredReg)  in FixInvalidRegPairOp()
1178                       Pred, PredReg, TII, isT2);  in FixInvalidRegPairOp()
1185                       Pred, PredReg, TII, isT2);  in FixInvalidRegPairOp()
1201                       Pred, PredReg, TII, isT2);  in FixInvalidRegPairOp()
1206                       Pred, PredReg, TII, isT2);  in FixInvalidRegPairOp()
1253       unsigned PredReg = 0;  in LoadStoreMultipleOpti()  local
1254       ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);  in LoadStoreMultipleOpti()
1272         CurrPredReg = PredReg;  in LoadStoreMultipleOpti()
1473                           unsigned &PredReg, ARMCC::CondCodes &Pred,
1568                                           int &Offset, unsigned &PredReg,  in CanFormLdStDWord()  argument
1630   Pred = getInstrPredicate(Op0, PredReg);  in CanFormLdStDWord()
1729         unsigned BaseReg = 0, PredReg = 0;  in RescheduleOps()  local
1737                                              Offset, PredReg, Pred, isT2)) {  in RescheduleOps()
1757             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()
1771             MIB.addImm(Offset).addImm(Pred).addReg(PredReg);  in RescheduleOps()
1826       unsigned PredReg = 0;  in RescheduleLoadStoreInstrs()  local
1827       if (getInstrPredicate(MI, PredReg) != ARMCC::AL)  in RescheduleLoadStoreInstrs()