100     bool isSub = false;  in emitThumbRegPlusImmInReg()  local
106       isSub = true;  in emitThumbRegPlusImmInReg()
128     int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);  in emitThumbRegPlusImmInReg()
133     if (DestReg == ARM::SP || isSub)  in emitThumbRegPlusImmInReg()
173   bool isSub = NumBytes < 0;  in emitThumbRegPlusImmediate()  local
175   if (isSub) Bytes = -NumBytes;  in emitThumbRegPlusImmediate()
189     Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;  in emitThumbRegPlusImmediate()
191   } else if (!isSub && BaseReg == ARM::SP) {  in emitThumbRegPlusImmediate()
211       Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;  in emitThumbRegPlusImmediate()
216       Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;  in emitThumbRegPlusImmediate()
240       const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);  in emitThumbRegPlusImmediate()
283         Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;  in emitThumbRegPlusImmediate()
347   bool isSub = Imm < 0;  in emitThumbConstant()  local
348   if (isSub) Imm = -Imm;  in emitThumbConstant()
358   if (isSub) {  in emitThumbConstant()